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| 型號： | 5962D1022901QXC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 40 SYNCHRONOUS DRAM, 5.4 ns, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 56/68頁 |
| 文件大小： | 1475K |
| 代理商： | 5962D1022901QXC |
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6
2.5G (512Mb x 5) SDRAM Module
Table 1. Pin Descriptions
Pin
Numbers
Symbols
Type
Description
77
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
79
CKE
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE power-down, ACTIVE power-down
(row active in any bank), or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down where CKE becomes
asynchronous until after exiting the same mode. The input buffers, including CLK, are
disabled during power-down providing low standby power. CKE may be tied HIGH.
80
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
78, 76, 75 RAS#,CAS#,
WE#
Input
Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered.
112, 16,
111, 59, 58
DQM(4:0)
Input
Input/output mask: DQM is an input mask signal for write accesses and an output
enable signal for read accesses. Input data is masked when DQM is sampled HIGH
during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQM is sampled HIGH during a READ cycle.
84 ,82
BA (1:0)
Input
Bank address inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE,
or PRECHARGE command is being applied.
81, 83, 86,
85, 87, 89,
91, 93, 95,
94, 92, 90,
88
A(12:0)
Input
Address inputs: A0–A12 are sampled during the ACTIVE command (row-address
A0–A12) and READ/WRITE command (column-address A0–A9, A11); with A10
defining auto precharge) to select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to determine whether all banks
are to be precharged (A10[HIGH]) or bank selected by (A10 [LOW]). The address inputs
also provide the opcode during a LOAD MODE REGISTER command.
42, 46, 50,
54, 56, 52,
48, 44
DQ[7.0](0)
Data I/O
Data input/output
43, 47, 51,
55, 57, 53,
49, 45
DQ[7:0](1)
Data I/O
Data input/output
127, 123,
119, 115,
113, 117,
121, 125
DQ[7:0](2)
Data I/O
Data input/output
32, 28, 24,
20, 18, 22,
26, 30
DQ[7:0](3)
Data I/O
Data input/output
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