參數(shù)資料
型號(hào): 514NCCXXXXXXBAGR
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 125 MHz, OTHER CLOCK GENERATOR, PDSO6
封裝: 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6
文件頁數(shù): 30/32頁
文件大?。?/td> 267K
代理商: 514NCCXXXXXXBAGR
Si514
Preliminary Rev. 0.9
7
Table 5. Output Clock Jitter and Phase Noise
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Period Jitter (RMS)
JPRMS
10 k samples1
——
1.2
ps
Period Jitter (Pk-Pk) JPPKPK
10 k samples1
——
11
ps
Phase Jitter (RMS)
φJ(rèn)
1.875 MHz to 20 MHz integration
bandwidth2 (brickwall)
—0.31
0.55
ps
12 kHz to 20 MHz integration
bandwidth2
—0.8
1.0
ps
Phase Noise,
156.25 MHz
φN
100 Hz
–85
dBc/Hz
1kHz
–110
dBc/Hz
10 kHz
–115
dBc/Hz
100 kHz
–120
dBc/Hz
1 MHz
–135
dBc/Hz
Additive RMS
Jitter Due to Power
Supply Noise3
JPSR
10 kHz sinusoidal noise
< 0.5
ps
100 kHz sinusoidal noise
1
ps
500 kHz sinusoidal noise
1
ps
1 MHz sinusoidal noise
1
ps
Spurious
SPR
LVPECL output, 156.25 MHz,
offset > 10 kHz
—–75
dBc
Notes:
1.
Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2.
Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3.
156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP, 1.8 V =
50 mVPP).
相關(guān)PDF資料
PDF描述
514PAAXXXXXXAAGR 250 MHz, OTHER CLOCK GENERATOR, PDSO6
514PAAXXXXXXBAGR 250 MHz, OTHER CLOCK GENERATOR, PDSO6
514PACXXXXXXAAGR 125 MHz, OTHER CLOCK GENERATOR, PDSO6
514PACXXXXXXAAG 125 MHz, OTHER CLOCK GENERATOR, PDSO6
514PACXXXXXXBAG 125 MHz, OTHER CLOCK GENERATOR, PDSO6
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