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參數(shù)資料
| 型號(hào)： | 514NCCXXXXXXBAGR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 125 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 封裝： | 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 267K |
| 代理商： | 514NCCXXXXXXBAGR |
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Si514
Preliminary Rev. 0.9
11
e. Register 9 = 0x09 (M_Int[8:3])
f. M_Int = 0b001001010 = 0x4A = 0d74
g. M_Frac = 0x097C65D3 = 159,147,475
h. M= M_Int + M_Frac/229 = 74 + 159,147,475/229 = 74.296435272321105
2. Calculate Mnew:
a. Mnew = 74.296435272321105 x 148.352/148.5 = 74.2223889933965
b. M_Intnew = 74 = 0x4A
c. M_Fracnew = 0.2223889933965 x 229 = 119,394,181 = 0x071DCF85
3. Write Mnew to Registers 5-7:
a. Register 5 = 0x85
b. Register 6 = 0xCF
c. Register 7 = 0x1D
4. Write Mnew to Register 8:
a. Register 8 = 0x47
5. Write Mnew to Register 9:
a. Register 9 = 0x09
2.3. Programming a Large Frequency Change (> ±1000 ppm)
Large frequency changes are those that vary the FVCO frequency by an amount greater than ±1000 ppm from an
operating FCENTER. Figure 2 illustrates the difference between large and small frequency changes. Changing from
FCENTER to F'CENTER requires a calibration cycle that resets internal circuitry to establish F'CENTER as the new
operating center frequency. The below steps are recommended when performing large frequency changes:
1. Disable the output: Write OE register bit to a 0 (Register 132, bit2)
2. If using one of the standard frequencies listed in Table 9, then write the new LP1, LP2, M_Frac, M_Int, HS_DIV
and LS_DIV register values according to the table (be sure to write M_Int[8:3] (Register 9) after writing to the
M_Frac registers (Registers 5-8)). Skip to Step 9. If the desired frequency is not in the table, then follow steps
4-8 below.
3. Determine the minimum value of LS_DIV (minimizing LS_DIV minimizes the number of dividers on the output
stage, thus minimizing jitter) according to the following formula:
a. LS_DIV = FVCO(MIN)/(FOUT x HS_DIV(MAX)) (Eq 2.6)
b. LS_DIV = 2080/(FOUT(MHz) x 1022) (Eq 2.7)
i. Since LS_DIV is restricted to: dividing by 1,2,4,8,16,32, choose the next largest value over the
result derived in Eq 2.7 (e.g., if result is 4.135, choose LS_DIV = 8)
4. Determine the minimum value for HS_DIV (this optimizes timing margins)
a. HS_DIV(MIN) = FVCO(MIN)/(FOUT x LS_DIV) (Eq 2.8)
b. HS_DIV(MIN) = 2080/(FOUT(MHz) x LS_DIV) (Eq 2.9)
i.HS_DIV(MIN) will be the next even number greater than or equal to the result derived in Eq 2.9
(keeping in the range of 10-1022)
Note:
SPEED_GRADE_MIN (Reg 48) ≤ LS_DIV x HS_DIV ≤ SPEED_GRADE_MAX (Reg 49); If outside this range, the output
will be forced to the disabled state.
5. Determine a value for M according to the following formula (all values are in decimal format):
a. M = LS_DIV x HS_DIV x FOUT/FXO (Eq 2.10)
b. M = LS_DIV x HS_DIV x FOUT(MHz)/31.98 (Eq 2.11)
c. M_Int = INT[M] (Eq 2.12)
d. M_Frac = (M – INT[M]) x 229 (Eq 2.13)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 514PAAXXXXXXAAGR | 250 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 514PAAXXXXXXBAGR | 250 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 514PACXXXXXXAAGR | 125 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 514PACXXXXXXAAG | 125 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 514PACXXXXXXBAG | 125 MHz, OTHER CLOCK GENERATOR, PDSO6 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 514P103212P | 制造商: 功能描述: 制造商:80205 功能描述: |
| 514P1032-12P | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 514P1032-14P | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 514P1032-8 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 514P1032-8B | 制造商: 功能描述: 制造商:undefined 功能描述: |
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