- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370034 > 28222-13 (Conexant Systems, Inc.) ATM Transmitter/Receiver with UTOPIA Interface PDF資料下載
參數(shù)資料
| 型號(hào)： | 28222-13 |
| 廠商： | Conexant Systems, Inc. |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | 自動(dòng)柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口 |
| 文件頁(yè)數(shù)： | 74/161頁(yè) |
| 文件大?。?/td> | 1832K |
| 代理商： | 28222-13 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)當(dāng)前第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)
to four levels. The control bits for setting the port priority level are in the
CELL_GEN_x control registers. Priority level 0 is the highest priority, priority
level 3 is the lowest (see
Table 2-26
).
2.0 Functional Description
CN8223
2.7 FIFO Port/UTOPIA Interface
ATM Transmitter/Receiver with UTOPIA Interface
2-40
Conexant
100046C
2.7.2 Transmit Port Priority Mechanism
Each of the four transmit data read ports has a priority level that is programmable
If more than one port is assigned the same priority level, then arbitration
occurs in port order with bandwidth allocated cyclically to Port 0, Port 1, Port 2,
and Port 3.
The priority state machine looks at the port empty flag inputs for all ports at
priority level 0 and reads cells from these ports cyclically until all port flags
indicate empty. If no cells are available at priority 0, the state machine then looks
at the port empty flags for all ports at priority level 1 and reads cells from these
ports cyclically as long as no priority 0 port has a cell ready.
Table 2-25. FIFO Receive Pin Descriptions
CN8223 FIFO Input
Functional Description
Receive Data Write Strobe
The receive data FIFO interface strobes data octets from FDAT_OUT[8:0] into an external
FIFO device on each rising edge of Receive Data Write Strobe. This strobe is a gated clock
with 48-, 52-, 53-, or 57- strobes for the corresponding number of cell octets, depending
on mode. There are four Receive Data Write Strobes, one per port.
Receive Data FIFO Full
This flag is active low. If Receive Data FIFO Full is asserted by the external FIFO and the
CN8223 attempts a write to that port data, loss occurs. If this happens, Receive FIFO Write
Error pin (FCTRL_OUT[10]) is asserted low. There are four Receive Data FIFO full signals,
one per port.
Receive Cell Sync Marker
The sync marker will be low during the last octet of data transfer and high during all other
octets of the data transfer for each cell regardless of the number of octets selected for
output.
Receive Cell Invalid Indication
This per-port signal indicates that a HEC or other check has failed. The invalid indication will
be low during the first octet of data transfer. If any enabled check fails, the invalid indication
will be high during the last five octets of the cell. If no failures occur, the indication will stay
de-asserted through the end of the cell. The FIFO or a microprocessor must mark this cell
as bad to prevent further processing.
Optional Start of Cell Mode
If Start-of-Cell/Write Error Output [bit 15] in the CELL_VAL register [0x14] is set, then
FCTRL_OUT[10] becomes an active-high start-of-cell output marker for the receiver, and
FCTRL_OUT[16] becomes an active-high start-of-cell output marker for the transmitter.
These indicators are valid only in 53-octet input/output mode. In this mode, the Receive
FIFO Write Error function is not available.
Table 2-26. Priority Levels
CELL_GEN 3
CELL_GEN 2
Priority Level
0
0
0
0
1
1
1
0
2
1
1
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28222-14 | ATM Transmitter/Receiver with UTOPIA Interface |
| 28233-11 | ATM Transmitter/Receiver with UTOPIA Interface |
| 28C010TRPDB-12 | 150 x 32 pixel format, LED Backlight available |
| 28C010TRT1DE-15 | 1 Megabit (128K x 8-Bit) EEPROM |
| 28C010TRT1DE-20 | 1 Megabit (128K x 8-Bit) EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28222-14 | 制造商:CONEXANT 制造商全稱:CONEXANT 功能描述:ATM Transmitter/Receiver with UTOPIA Interface |
| 282222-003 | 制造商:TE Connectivity 功能描述:81044/12-16-2 - Cable Rools/Shrink Tubing |
| 282223-003 | 制造商:TE Connectivity 功能描述:81044/12-16-3 - Cable Rools/Shrink Tubing |
| 282224-003 | 制造商:TE Connectivity 功能描述:81044/12-16-4 - Cable Rools/Shrink Tubing |
| 282224-1 | 功能描述:汽車連接器 ECONOSEAL RCPT CONT .5MM RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類型: 觸點(diǎn)電鍍:Nickel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。