參數(shù)資料
型號(hào)： 28222-13
廠商： Conexant Systems, Inc.
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： 自動(dòng)柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口
文件頁數(shù)： 115/161頁
文件大?。?/td> 1832K
代理商： 28222-13
CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.7 Status Register Overview
100046C
Conexant
3-29
0x38
—
LINE_STATUS (Line Framer/PHY Interrupt Status Register)
The LINE_STATUS register is located at address 0x38. Bit definitions for this register depend on the line
interface mode selected. LINE_STATUS indicates alarms, errors, and framing states of the CN8223 line
receivers. For 53-octet formats that use external framers or the parallel input, the only meaningful bit is the LOC
indication (bit 8). LINE_STATUS interrupts appear on STAT_INT, if they are enabled by writing the desired
bits in EN_LINE_INT. LINE_STATUS bits are set regardless of whether interrupts are enabled.
Each LINE_STATUS bit is latched until read and then cleared if the condition is no longer present. If a status
condition clears before the register is read, the status bit will still be held. Current status can be obtained by
reading the register twice in succession. Upper and lower bytes of LINE_STATUS operate differently in regard
to interrupt generation. Upper definitions of LINE_STATUS (bits 15
–
9) are events that generate an interrupt
when the event occurs (for example, if Line FERF [bit 9] in STS-3c mode occurs, a single interrupt will be
generated when the Line FERF occurs).
The lower definitions of LINE_STATUS (bits 8
–
0) are level-sensitive conditions, meaning interrupts occur
on any change of state. For example, when LOS occurs in STS-3c mode, an interrupt occurs. When LOS goes
away, a second interrupt occurs. The contents of the LINE_STATUS register are the logical OR of the status
event, for instance, OOF and STAT_INT line. In SONET/SDH or G.832 E3/E4 modes, bits 9, 12, and 13 also
become level-sensitive.
Two examples of this are given:
Example 1: If the line is disconnected, the OOF interrupt goes active. Reading the LINE_STATUS
register causes the STAT_INT line (pin 64) to go inactive. Reading the LINE_STATUS
register again continues to show the OOF condition that caused the interrupt. Reconnecting
the line causes another interrupt. Reading the LINE_STATUS register will cause the
STAT_INT line to go inactive and show OOF active. (OOF will show active because the
contents of LINE_STATUS are the logical OR of OOF and the STAT_INT line. See
waveform in
Figure 3-1
.) Reading the LINE_STATUS register again will show OOF
inactive.
Example 2: If the line is disconnected, OOF will again go active. If you reconnect the line before the
LINE_STATUS register is read, the STAT_INT line will go active. Reading the
LINE_STATUS register will show OOF active and cause STAT_INT line to go inactive.
Reading LINE_STATUS register again will show OOF in the inactive state because the line
was reconnected.
Table 3-12
lists STS-1, STS-3c, and STM-1 LINE_STATUS bit definitions.
Figure 3-1. LINE_STATUS and OOF Example
OOF
Contents of the LINE_STATUS register
STAT_INT line
Read LINE_STATUS
Read LINE_STATUS
8
相關(guān)PDF資料
PDF描述
28222-14 ATM Transmitter/Receiver with UTOPIA Interface
28233-11 ATM Transmitter/Receiver with UTOPIA Interface
28C010TRPDB-12 150 x 32 pixel format, LED Backlight available
28C010TRT1DE-15 1 Megabit (128K x 8-Bit) EEPROM
28C010TRT1DE-20 1 Megabit (128K x 8-Bit) EEPROM
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參數(shù)描述
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