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參數(shù)資料
| 型號： | 21041 |
| 廠商： | Intel Corp. |
| 英文描述： | Digital Semiconductor 21041 PCI Ethernet LAN Controller(數(shù)字半導體21041 PCI以太網(wǎng)LAN控制器) |
| 中文描述： | 數(shù)字半導體21041 PCI以太網(wǎng)局域網(wǎng)控制器（數(shù)字半導體21041的PCI以太網(wǎng)局域網(wǎng)控制器） |
| 文件頁數(shù)： | 24/64頁 |
| 文件大?。?/td> | 230K |
| 代理商： | 21041 |
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Table 4 (Cont.) Quick Pin Reference
Signal
Type
Pin
Number
Description
perr_l
I/O
47
Parity error asserts when a data parity error
is detected.
When the 21041 is the bus initiator and a
parity error is detected, the 21041 asserts
both CSR5 bit 13 (system error) and CFCS
bit 9 (
serr_l
enable) and completes the
current data burst transaction, then stops
its operation. After the host clears the system
error, the 21041 continues its operation.
When the 21041 is the bus target and a parity
error is detected, the 21041 asserts
perr_l
.
Bus request is asserted by the 21041 to
indicate to the bus arbiter that it wants to use
the bus.
Resets the 21041 to its initial state. This
signal must be asserted for at least 10 active
PCI clock cycles. When in the reset state, all
PCI port output pins are put into tristate and
all open drain (O/D) signals are floated.
If an address parity error is detected and
CFCS bit 31 (detected parity error) is enabled,
then 21041 asserts both
serr_l
(system error)
and CFCS bit 30 (signal system error).
When an address parity error is detected,
system error asserts two clocks after the
failing address.
When deasserted, this pin should be pulled up
by an external resistor.
Serial ROM chip select asserts when the
21041 accesses the serial ROM.
Stop indicator indicates that the current
target is requesting the bus initiator to stop
the current transaction.
The 21041 responds to the assertion of
stop_l
when it is the bus initiator, either
to disconnect, retry, or abort.
(continued on next page)
req_l
O
12
rst_l
I
6
serr_l
O/D
49
sr_cs
O
81
stop_l
I/O
46
16
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