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參數(shù)資料
| 型號(hào)： | 21041 |
| 廠商： | Intel Corp. |
| 英文描述： | Digital Semiconductor 21041 PCI Ethernet LAN Controller(數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)LAN控制器) |
| 中文描述： | 數(shù)字半導(dǎo)體21041 PCI以太網(wǎng)局域網(wǎng)控制器（數(shù)字半導(dǎo)體21041的PCI以太網(wǎng)局域網(wǎng)控制器） |
| 文件頁數(shù)： | 22/64頁 |
| 文件大?。?/td> | 230K |
| 代理商： | 21041 |
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Table 4 (Cont.) Quick Pin Reference
Signal
Type
Pin
Number
Description
devsel_l
I/O
45
The 21041 asserts device select when it is
the target of the current bus access. When
the 21041 is the initiator of the current bus
access, it expects the target to assert
devsel_l
within 5 bus cycles, confirming the access. To
accomplish this, the 21041 asserts this signal
in a medium speed (within two bus cycles). If
the target does not assert
devsel_l
within the
required bus cycles, then the 21041 aborts the
cycle.
Frame is driven by the 21041 (bus initiator)
to indicate the beginning and duration of an
access. When
frame_l
asserts, it indicates
the beginning of a bus transaction. While
frame_l
is asserted, data transfers continue.
When
frame_l
is deasserted, it indicates that
the next data phase is the final data phase
transaction.
Bus grant asserts to indicate to the 21041
that access to the bus is granted.
Initialization device select asserts to act as a
chip select during configuration read or write
transactions.
Interrupt request asserts when one of the
appropriate bits of CSR5 sets and causes an
interrupt, provided that the corresponding
mask bit in CSR7 is not asserted. The
int_l
deasserts by writing a 1 into the appropriate
CSR5 bit.
If more than one interrupt bit is asserted in
CSR5, then the host clears only the interrupt
bit that was acknowledged,
int_l
deasserts
for one cycle and then asserts again. This
process continues until all interrupts are
acknowledged.
When deasserted, this pin should be pulled up
by an external resistor.
(continued on next page)
frame_l
I/O
41
gnt_l
I
11
idsel
I
26
int_l
O/D
5
14
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