參數資料
型號： 1893YI-10
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 網絡接口
英文描述： DATACOM, INTERFACE CIRCUIT, PQFP64
封裝： 10 X 10 MM, TQFP-64
文件頁數： 87/152頁
文件大?。?/td> 943K
代理商： 1893YI-10
ICS1893 Rev C 6/6/00
June, 2000
4
Table of Contents
ICS1893 Data Sheet - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Table of Contents
Section
Title
Page
Chapter 8
Management Register Set ............................................................................................... 59
8.1
Introduction to Management Register Set ............................................................. 60
8.1.1
Management Register Set Outline ......................................................................... 60
8.1.2
Management Register Bit Access .......................................................................... 61
8.1.3
Management Register Bit Default Values .............................................................. 61
8.1.4
Management Register Bit Special Functions ......................................................... 62
8.2
Register 0: Control Register ................................................................................... 63
8.2.1
Reset (bit 0.15) ...................................................................................................... 63
8.2.2
Loopback Enable (bit 0.14) .................................................................................... 64
8.2.3
Data Rate Select (bit 0.13) ..................................................................................... 64
8.2.4
Auto-Negotiation Enable (bit 0.12) ......................................................................... 64
8.2.5
Low Power Mode (bit 0.11) .................................................................................... 65
8.2.6
Isolate (bit 0.10) ..................................................................................................... 65
8.2.7
Restart Auto-Negotiation (bit 0.9) .......................................................................... 65
8.2.8
Duplex Mode (bit 0.8) ............................................................................................. 66
8.2.9
Collision Test (bit 0.7) ............................................................................................ 66
8.2.10
IEEE Reserved Bits (bits 0.6:0) ............................................................................. 66
8.3
Register 1: Status Register .................................................................................... 67
8.3.1
100Base-T4 (bit 1.15) ............................................................................................ 67
8.3.2
100Base-TX Full Duplex (bit 1.14) ......................................................................... 68
8.3.3
100Base-TX Half Duplex (bit 1.13) ........................................................................ 68
8.3.4
10Base-T Full Duplex (bit 1.12) ............................................................................. 68
8.3.5
10Base-T Half Duplex (bit 1.11) ............................................................................. 68
8.3.6
IEEE Reserved Bits (bits 1.10:7) ........................................................................... 69
8.3.7
MF Preamble Suppression (bit 1.6) ....................................................................... 69
8.3.8
Auto-Negotiation Complete (bit 1.5) ....................................................................... 69
8.3.9
Remote Fault (bit 1.4) ............................................................................................ 70
8.3.10
Auto-Negotiation Ability (bit 1.3) ............................................................................ 70
8.3.11
Link Status (bit 1.2) ................................................................................................ 71
8.3.12
Jabber Detect (bit 1.1) ........................................................................................... 71
8.3.13
Extended Capability (bit 1.0) .................................................................................. 71
8.4
Register 2: PHY Identifier Register ........................................................................ 72
相關PDF資料
PDF描述
1894-40KLF DATACOM, INTERFACE CIRCUIT, QCC40
1894-40KLFT DATACOM, INTERFACE CIRCUIT, QCC40
1895230000 15 A, STRIP TERMINAL BLOCK, 2 ROWS, 2 DECKS
18F-08P-241 8 CONTACT(S), CABLE MOUNT, MINI DIN CONNECTOR, PLUG
18F-08P-244 8 CONTACT(S), CABLE MOUNT, MINI DIN CONNECTOR, PLUG
相關代理商/技術參數
參數描述
1893YI-10LF 功能描述:以太網 IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
1893YI-10LFT 功能描述:以太網 IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產品:Ethernet Switches 收發(fā)器數量:2 數據速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
1894 功能描述:支架與墊片 HEX .187X.625 ALUM RoHS:否 制造商:Schurter 類型:Transipillar Spacers 長度:16 m 螺紋大小:M4 外徑:10 mm 材料:Nylon with Steel 電鍍:Zinc
1894# 制造商:Fluke Electronics 功能描述:BNC (F)/BANANA PLUG 制造商:Pomona Electronics 功能描述:
1894 制造商:Pomona Electronics 功能描述:ADAPTER BNC FEMALE-BANANA PLUG 制造商:Pomona Electronics 功能描述:ADAPTER, BNC FEMALE-BANANA PLUG
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*