- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄293745 > 1893YI-10 (INTEGRATED DEVICE TECHNOLOGY INC) DATACOM, INTERFACE CIRCUIT, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | 1893YI-10 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | DATACOM, INTERFACE CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, TQFP-64 |
| 文件頁數(shù)： | 115/152頁 |
| 文件大小： | 943K |
| 代理商： | 1893YI-10 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁當(dāng)前第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁
Chapter 8
Management Register Set
ICS1893 Rev C 6/6/00
June, 2000
65
ICS1893 - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
8.2.5
Low Power Mode (bit 0.11)
This bit provides one way to control the ICS1893 low-power mode function. When bit 0.11 is logic:
Zero, there is no impact to ICS1893 operations.
One, the ICS1893 enters the low-power mode. In this case, the ICS1893 disables all internal functions
and drives all MAC/repeater output pins low except for those that support the MII Serial Management
Port. In addition, the ICS1893 internally activates the TPTRI function to tri-state the signals on the
Twisted-Pair Transmit pins (TP_TXP and TP_TXN) and achieve additional power savings.
Note:
There are two ways the ICS1893 can enter low-power mode. When entering low-power mode:
By setting bit 0.11 to logic one, the ICS1893 maintains the value of all Management Register bits
except the latching high (LH) and latching low (LL) status bits, which are re-initialized to their
default values instead. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits”and Section 8.1.4.2, “Latching Low Bits”.)
During a reset, the ICS1893 sets all management register bits to their default values.
8.2.6
Isolate (bit 0.10)
This bit controls the ICS1893 Isolate function. When bit 0.10 is logic:
Zero, there is no impact to ICS1893 operations.
One, the ICS1893 electrically isolates its data paths from the MAC/Repeater Interface. The ICS1893
places all MAC/repeater output signals (TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS) in a
high-impedance state and it isolates all MAC/repeater input signals (TXD[3:0], TXEN, and TXER). In this
mode, the Serial Management Interface continues to operate normally (that is, bit 0.10 does not affect
the Management Interface).
The default value for bit 0.10 depends upon the PHY address of Table 8-16. If the PHY address:
Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893 isolates itself from the
MAC/Repeater Interface.
Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893 does not isolate
its MAC/Repeater Interface.
8.2.7
Restart Auto-Negotiation (bit 0.9)
This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is
logic one). When bit 0.12 is logic:
Zero, the Auto-Negotiation sublayer is disabled, and the ICS1893 isolates any attempt by the STA to set
bit 0.9 to logic one.
One (as set by an STA), the ICS1893 restarts the auto-negotiation process. Once the auto-negotiation
process begins, the ICS1893 automatically sets this bit to logic zero, thereby providing the self-clearing
feature.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 1894-40KLF | DATACOM, INTERFACE CIRCUIT, QCC40 |
| 1894-40KLFT | DATACOM, INTERFACE CIRCUIT, QCC40 |
| 1895230000 | 15 A, STRIP TERMINAL BLOCK, 2 ROWS, 2 DECKS |
| 18F-08P-241 | 8 CONTACT(S), CABLE MOUNT, MINI DIN CONNECTOR, PLUG |
| 18F-08P-244 | 8 CONTACT(S), CABLE MOUNT, MINI DIN CONNECTOR, PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 1893YI-10LF | 功能描述:以太網(wǎng) IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 1893YI-10LFT | 功能描述:以太網(wǎng) IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 1894 | 功能描述:支架與墊片 HEX .187X.625 ALUM RoHS:否 制造商:Schurter 類型:Transipillar Spacers 長度:16 m 螺紋大小:M4 外徑:10 mm 材料:Nylon with Steel 電鍍:Zinc |
| 1894# | 制造商:Fluke Electronics 功能描述:BNC (F)/BANANA PLUG 制造商:Pomona Electronics 功能描述: |
| 1894 | 制造商:Pomona Electronics 功能描述:ADAPTER BNC FEMALE-BANANA PLUG 制造商:Pomona Electronics 功能描述:ADAPTER, BNC FEMALE-BANANA PLUG |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。