參數(shù)資料
型號(hào): 1893YI-10
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: DATACOM, INTERFACE CIRCUIT, PQFP64
封裝: 10 X 10 MM, TQFP-64
文件頁數(shù): 120/152頁
文件大?。?/td> 943K
代理商: 1893YI-10
Table of Contents
ICS1893 Rev C 6/6/00
June, 2000
7
ICS1893 - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Table of Contents
Section
Title
Page
8.14
Register 19: Extended Control Register 2 ........................................................... 100
8.14.1
Node/Repeater Configuration (bit 19.15) ............................................................. 101
8.14.2
Hardware/Software Priority Status (bit 19.14) ...................................................... 101
8.14.3
Remote Fault (bit 19.13) ...................................................................................... 101
8.14.4
ICS Reserved (bits 19.12:8) ................................................................................. 101
8.14.5
Twisted Pair Tri-State Enable, TPTRI (bit 19.7) ................................................... 102
8.14.6
ICS Reserved (bits 19.12:6) ................................................................................. 102
8.14.7
Force LEDs On (bit 19.5) ..................................................................................... 102
8.14.8
ICS Reserved (bits 19.4:1) ................................................................................... 102
8.14.9
Automatic 100Base-TX Power-Down (bit 19.0) ................................................... 102
Chapter 9
Pin Diagram, Listings, and Descriptions ..................................................................... 103
9.1
ICS1893 Pin Diagram .......................................................................................... 103
9.2
ICS1893 Pin Listings ............................................................................................ 104
9.3
ICS1893 Pin Descriptions .................................................................................... 105
9.3.1
Transformer Interface Pins .................................................................................. 105
9.3.2
Multi-Function (Multiplexed) Pins: PHY Address and LED Pins .......................... 106
9.3.3
Configuration Pins ................................................................................................ 110
9.3.4
MAC/Repeater Interface Pins .............................................................................. 112
9.3.5
Reserved Pins ...................................................................................................... 121
9.3.6
Ground and Power Pins ....................................................................................... 122
Chapter 10
DC and AC Operating Conditions............................................................................... 123
10.1
Absolute Maximum Ratings ................................................................................. 123
10.2
Recommended Operating Conditions .................................................................. 123
10.3
Recommended Component Values ..................................................................... 124
10.4
DC Operating Characteristics .............................................................................. 125
10.4.1
DC Operating Characteristics for Supply Current ................................................ 125
10.4.2
DC Operating Characteristics for TTL Inputs and Outputs .................................. 125
10.4.3
DC Operating Characteristics for REF_IN ........................................................... 126
10.4.4
DC Operating Characteristics for Media Independent Interface .......................... 126
10.5
Timing Diagrams .................................................................................................. 127
10.5.1
Timing for Clock Reference In (REF_IN) Pin ....................................................... 127
10.5.2
Timing for Transmit Clock (TXCLK) Pins ............................................................. 128
10.5.3
Timing for Receive Clock (RXCLK) Pins .............................................................. 129
10.5.4
100M MII / 100M Stream Interface: Synchronous Transmit Timing ..................... 130
10.5.5
10M MII: Synchronous Transmit Timing .............................................................. 131
10.5.6
MII / 100M Stream Interface: Synchronous Receive Timing ................................ 132
10.5.7
MII Management Interface Timing ....................................................................... 133
10.5.8
10M Serial Interface: Receive Latency ................................................................ 134
10.5.9
10M Media Independent Interface: Receive Latency ........................................... 135
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