參數(shù)資料
型號： 100-1221-3
廠商： Bluetechnix
文件頁數(shù)： 49/68頁
文件大?。?/td> 0K
描述： CORE MOD CM-BF537E 600MHZ CONN
標(biāo)準(zhǔn)包裝： 1
模塊/板類型： 核心模塊
其它名稱： 100-1221
100-1221-ND
Rev. J
|
Page 53 of 68
|
February 2014
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 50). Figure 51 through Figure 60 on
Page 55 show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
Figure 50. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
T1
ZO = 50
Ω (impedance)
TD = 4.04
± 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
Ω
0.5pF
70
Ω
400
Ω
45
Ω
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
Ω
Figure 51. Typical Output Delay or Hold for Driver A at VDDEXT Min
Figure 52. Typical Output Delay or Hold for Driver A at VDDEXT Max
LOAD CAPACITANCE (pF)
RISE TIME
RISE
AND
F
ALL
TIME
ns
(10
%t
o
90%)
14
12
10
8
6
4
2
0
50
100
150
200
250
FALL TIME
LOAD CAPACITANCE (pF)
RISE TIME
RIS
E
AND
F
ALL
TIME
ns
(10
%
to
90%)
12
10
8
6
4
2
0
50
100
150
200
250
FALL TIME
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