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參數資料
| 型號： | μPD98402A |
| 廠商： | NEC Corp. |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 9/26頁 |
| 文件大?。?/td> | 178K |
| 代理商： | ΜPD98402A |
μ
PD98402A
9
Power supply
Symbol
Pin No.
I/O
Function
V
DD
1, 20, 33, 40,
52, 55, 57, 60,
81, 100, 120,
137, 150
–
Supply voltage, 5 V
±
5 %
GND
21, 34, 41, 42,
47, 51, 56, 61,
64, 68, 72, 79,
80, 94, 101,
107, 113, 121,
122, 128, 138,
140, 147, 149,
159, 160
–
Ground
ATM Layer Interface
Symbol
Pin No.
I/O
I/O Level
Function
RDO0-RDO7
151-158
O
CMOS
Connected to 8-bit data bus to output the receive data to the
ATM Layer device. Output is synchronized with the RCLK
rising up. To be undefined after reset.
RCLK
148
I
TTL
Input pin of the receive data transferring clock from the ATM
Layer device.
RSOC
145
O
CMOS
Receive cell start address signal. To the ATM Layer device,
this signal indicates the start address byte of the receive ATM
cell. To be undefined after reset.
RENBL
146
I
TTL
Receive enable signal. Input pin of the signal indicating that
the ATM layer device can receive data.
EMPTY
144
O
CMOS
Output buffer empty signal. This signal indicates that there is
no data to be transferred to the receive FIFO of the
μ
PD98402A. To be inactive after reset.
TDI0-TDI7
129-136
I
TTL
8-bit data bus to input the transmit data from the ATM Layer
device. Reading a data on the bus is synchronized with the
TCLK rising-up.
TCLK
139
I
TTL
Input pin of the transmit data transferring clock from the ATM
layer device.
TSOC
142
I
TTL
Transmit cell start address signal. Input pin of the signal
indicating the start byte of the transmit ATM cell input from the
ATM Layer device to the
μ
PD98402A.
TENBL
141
I
TTL
Transmit enable signal. This signal indicates that the ATM
Layer device is transmitting the valid data to the TDI0-TDI7.
FULL
143
O
CMOS
Input buffer full signal. When 4 bytes remain as the
acceptable bytes of transmit FIFO at last, this signal changes
to active. To be inactive after reset.
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