![](http://datasheet.mmic.net.cn/380000/-PD98402A_datasheet_16745022/-PD98402A_10.png)
μ
PD98402A
10
Management Interface
Symbol
Pin No.
I/O
I/O Level
Function
D0-D7
104-106
108-112
I/O
CMOS
8-bit data bus for data transfer between the control processor
and the internal register of the
μ
PD98402A.
A0-A5
114-119
I
TTL
Address bus. Used for setting the internal register address of
the
μ
PD98402A.
R/W
123
I
TTL
Read/write control signal.
Low level: Write cycle
High level: Read cycle
CE
126
I
TTL
Chip enable signal.
At low level, internal register access is to be enable.
ACK
124
O
CMOS
Read/write cycle receive acknowledge or ready signal.
After reset, this signal indicates inactive level.
PHINT
127
O
CMOS
Signal which indicates the interrupt cause occurrence to the
processor.
After reset, this signal indicates inactive level.
OE
125
I
TTL
Output enable. When this signal is set to low level, the
μ
PD98402A outputs data to the control bus. Even if the CE
signal is inactive, when this signal is at low level, the
μ
PD98402A drives the control bus.
OAM Interface
Symbol
Pin No.
I/O
I/O Level
Function
LOS
9
O
CMOS
Loss of signal detection. Output high level when receive serial
data input is "0" for 50
μ
s continuously or optical input stop
signal (RAL) is input. When 2 consecutive frames of valid
synchronous pattern is detected, or when input of the optical
input stop signal is released, low level is output. To be
inactive after reset.
OOF
10
O
CMOS
Out of frame detection. When 4 consecutive frames of wrong
synchronous pattern are detected, high level is output. When
2 consecutive frames of normal synchronous pattern are
detected, low level is output. To be inactive after reset.
RAL
7
I
TTL
Receive alarm. Inputs receiver-side optical input stop signal
by the optical module.
Low level: Normal
High level: Optical input stopped.
TAL
8
I
TTL
Transmit alarm. Inputs transmit-side optical output stop signal
output by the optical module.
Low level: Normal
High level: Optical output stopped.