參數(shù)資料
型號(hào)： μPD9210FGC-7EA
廠商： NEC Corp.
英文描述： USB Host Controller(USB主控制器)
中文描述： USB主機(jī)控制器（的USB主控制器）
文件頁(yè)數(shù)： 63/95頁(yè)
文件大?。?/td> 423K
代理商： ΜPD9210FGC-7EA
CHAPTER 5 REGISTER INFORMATION
63
Remarks 1.
Be sure to use REQ_Enable the default. If used asynchronously, it may no longer comply with the
PCI specifications.
2.
The Power State bit is invalid when PC_mode = 0. The system has read/write access to the Power
State bit. The HC has read-only access.
3.
The Wakeup_Status bit is invalid when PC_mode = 0. When PC_mode = 1, Power State = 10, and
HCFS = U
SB
S
USPEND
, “1” is set when a RESUME signal from the USB is detected. At that point, if
the Wakeup_Enable bit = 1, the WAKE signal is asserted. Writing “1” clears this bit and
simultaneously deasserts WAKE. The above operations occur only when the HcInterruptEnable
register’s RHSC/RD bit has been set.
4.
The Wakeup_Enable bit is invalid when PC_mode = 0.
5.
After the Power State bit has been set as D2 or D3, “0” is output as the Status Change Standby
value until the state transition is actually ready to occur, after which “1” is output. Once the Status
Change Standby value becomes “1” after the Power State bit has been set as D2 or D3, it does not
revert back to “0”. This bit’s value is always “0” when the Power State bit has been set as D0.
6.
The Bus Master Control bit switches the command register’s bus master bit’s valid/invalid setting.
When the Bus Master Control bit’s value is “0”, bus master operations are valid whether or not the
bus master bit’s value is set to “0”.
Figure 5-1. OpenHCI’s PCI Configuration Space
…
COMMAND
…
PCI Device
CLASS_CODE
…
BAR_OHCI
…
Mode
Operational
Registers
OpenHCI
HCCA
Status
Event
Frame Int
Ratio
Control
Bulk
Interrupt 0
Host Controller
Communications Area
Device Register
in memory space
Shared RAM
Interrupt 1
…
Interrupt 2
Interrupt 31
…
Done
The PCI Configuration Space’s Base Address (BAR_OHCI) Register is in an OpenHCI-compliant host controller.
It indicates the base address of Operational Registers which are the starting point for communication with the host
CPU.
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