參數(shù)資料
型號(hào)： μPD9210FGC-7EA
廠商： NEC Corp.
英文描述： USB Host Controller(USB主控制器)
中文描述： USB主機(jī)控制器（的USB主控制器）
文件頁(yè)數(shù)： 52/95頁(yè)
文件大?。?/td> 423K
代理商： ΜPD9210FGC-7EA
CHAPTER 4 POWER MANAGEMENT
52
4.2 Bus States and Device States
In this device, power management provides separate control of PCI and USB operations. Therefore, to
understand these operations, one must first understand the PCI bus states, USB bus states, and device states.
(1) PCI bus states
B0: PCI CLK = 33 MHz (includes CLKRUN operations)
B1: PCI CLK = Intermittent clock operation mode
B2: PCI CLK = Stop, PCI BUS power on
B3: PCI CLK = Stop, PCI BUS power off
(2) USB bus states
USB_Reset: Bus = Reset, USB system is stopped (except for state transition monitoring)
This state is entered when reset mode is canceled. This state can also be entered based on USB Operational
Register settings.
USB_Operational: Bus = Active, USB system is operating normally
This state can be entered based on USB Operational Register settings.
USB_Suspend: Bus = Suspend, USB system is stopped (except for bus state and state transition monitoring)
This state can be entered based on USB Operational Register settings. The state transition can also be
caused by S/W_Reset.
USB_Resume: Bus = Resume, USB system is operating normally
This state can be entered based on USB Operational Register settings. The state transition can also be
caused by connecting or disconnecting devices or by a Wakeup request from a connected device.
(3) Device states
D0 :
Normal operation mode (PCI = B0, USB = RESET, OPERATIONAL, SUSPEND, or RESUME)
The PCI state must be B0, USB state can be any state.
Device sleep mode (PCI = B0, B1, or B2; USB = RESET, SUSPEND/RESUME)
The PCI state can be normal operation, intermittent operation, or suspended operation, but the CPU can
access the HC's configuration space and operational registers only during the normal operation state.
This restriction exists in order to maintain synchronous periods between the HC and the HCD. The system
software and HCD should be coordinated to provide contrast so as to prevent HC operation faults. While
in this mode, if the USB state is SUSPEND, a Wakeup operation occurs if a new device connection or
disconnection is detected or if the RESUME state is entered in response to a RESUME signal.
Device disable mode (PCI clock stop, USB = RESET, or power off)
The PCI state can be normal operation, intermittent operation, or suspended operation, but the CPU can
access the HC's configuration space and operational registers only during the normal operation state.
This restriction exists in order to maintain synchronous periods between the HC and the HCD. The system
software and HCD should be coordinated to provide contrast so as to prevent HC operation faults.
Wakeup operations do not occur.
D2 :
D3 :
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