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參數(shù)資料
| 型號： | μPD78P0208 |
| 廠商： | NEC Corp. |
| 英文描述： | 8 Bit Single Chip Microcontrollers(8位單片微控制器) |
| 中文描述： | 8位單片機微控制器（8位單片微控制器） |
| 文件頁數(shù)： | 38/72頁 |
| 文件大?。?/td> | 424K |
| 代理商： | ΜPD78P0208 |
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38
m
PD78P0208
DC CHARACTERISTICS (T
A
= –40 to +85 °C, V
DD
= 2.7 to 5.5 V)
Notes 1.
For P110 to P117 and P120 to P127, a high-level input leakage current of 50
m
A (MAX.) flows only during
the 1.5 clocks (no-wait time) after an instruction has been executed to read out ports 11, 12 (P11, P12)
or port mode registers 11, 12 (PM11, PM12). Outside the period of 1.5 clocks following executing a read-
out instruction, the current is 3
m
A (MAX.).
2.
For P110 to P117 and P120 to P127, a high-level input leakage current of 30
m
A (MAX.) flows only during
the 1.5 clocks (no-wait time) after an instruction has been executed to read out P11, P12, PM11, and PM12.
Outside the period of 1.5 clocks following executing a read-out instruction, the current is 3
m
A (MAX.).
Remark
Unless otherwise specified, shared pin characteristics are the same as port pin characteristics.
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
P10 to P17, P30 to P32, P35 to P37
P100 to P107, P110 to P117, P120 to P127
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
V
DD
V
DD
15
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
0.3V
DD
0.2V
DD
0.3V
DD
0.2V
DD
0.4
0.2V
DD
0.1V
DD
0.3V
DD
0.3V
DD
2.0
0.4
0.2V
DD
0.5
3
20
80
3
Note 1
3
Note 2
P21, P23
P70 to P74
X1, X2
XT1/P04, XT2
P10 to P17, P30 to P32, P35 to
P37
P100 to P107, P110 to P117,
P120 to P127
P21, P23
P70 to P74
X1, X2
XT1/P04, XT2
P30 to P37, P70 to P74
P01 to P03, P10 to P17, P20 to
P27
SB0, SB1, SCK0
I
OL
= 400
m
A
V
IN
= V
DD
V
IN
= 15 V
P110 to P117, P120 to P127
V
IN
= V
DD
V
IH1
V
IH2
V
IH3
V
IH4
V
IH5
V
IH6
V
IH7
V
IL1
V
IL2
V
IL3
V
IL4
V
IL5
V
IL6
V
IL7
V
OH
V
OL1
V
OL2
V
OL3
I
LIH1
I
LIH2
I
LIH3
I
LIH4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
m
A
m
A
m
A
m
A
m
A
Parameter
Symbol
Conditions
Min.
Typ.
Unit
Max.
0.7V
DD
0.8V
DD
0.7V
DD
V
DD
– 0.5
0.8V
DD
0.9V
DD
0.65V
DD
0.7V
DD
0.7V
DD
V
DD
– 0.5
0
0
0
0
0
0
0
0
V
DD
– 40
V
DD
– 1.0
V
DD
– 0.5
High-level input
voltage
Low-level input
voltage
High-level output
voltage
Low-level output
voltage
High-level input
leakage
N-ch open-drain
V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V,
I
OH
= –1 mA
I
OH
= –100
m
A
V
DD
= 4.5 to 5.5 V
I
OL
= 15 mA
V
DD
= 4.5 to 5.5 V
I
OL
= 1.6 mA
V
DD
= 4.5 to 5.5 V
With open-drain and
pull-up (R = 1 k
W
)
P00 to P03, P10 to
P17, P20 to P27,
P30 to P37, P70 to
P74, RESET
X1, X2, XT1/P04,
XT2
P70 to P74
V
DD
= 4.5 to 5.5 V
P01 to P03, P10 to P17, P20 to P27,
P30 to P37, P80 to P87, P90 to P97,
P100 to P107, P110 to P117, P120
to P127, FIP0 to FIP12
0.4
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