參數(shù)資料
型號(hào): μPD78F9217Y
廠商: NEC Corp.
英文描述: 8 Bit Single Chip Microcontrollers(8 位單片微控制器)
中文描述: 8位單片機(jī)微控制器(8位單片微控制器)
文件頁(yè)數(shù): 83/148頁(yè)
文件大小: 621K
代理商: ΜPD78F9217Y
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Preliminary Product Information
83
μ
PD78F9217Y
(b) SMB status register 0 (SMBS0)
This register indicates the SMB status.
SMBS0 is manipulated with a 1-bit or 8-bit memory manipulation instruction. SMBS0 is a read-only
register.
A RESET input clears SMBS0 to 00H.
Figure 7-39. Format of SMB Status Register 0 (1/3)
MSTS0
0
1
Clear conditions (MSTS0 = 0)
Cleared upon detection of stop condition
Cleared when ALD0 = 1
Cleared when LREL0 = 1
Cleared when SMBE0 changes from 1 to 0
Cleared by RESET input
Set conditions (MSTS0 = 1)
Set during generation of start condition
Master status
Slave status or communication wait status
Master transmission status
EXC0
0
1
Clear conditions (EXC0 = 0)
Cleared upon detection of start condition
Cleared upon detection of stop condition
Cleared when LREL0 = 1
Cleared when SMBE0 changes from 1 to 0
Cleared by RESET input
Extension code receive detection
Does not receive extension code.
Receives extension code.
ALD0
0
1
Clear conditions (ALD0 = 0)
Automatically cleared after reading SMBS0
Note
Cleared when SMBE0 changes from 1 to 0
Cleared by RESET input
Set conditions (ALD0 = 1)
Set upon defeat in arbitration
Arbitration defeat detection
No arbitration, or won in arbitration.
Defeated in arbitration. MSTS0 cleared.
Set conditions (EXC0 = 1)
Set when high-order 4 bits of received address are
0000 or 1111 (set at rising edge of 8th clock)
MSTS0
ALD0
EXC0
COI0
TRC0
ACKD0
STD0
SPD0
SMBS0
7
6
5
4
Symbol
Address
When reset
R/W
FF79H
00H
R
3
2
1
0
Note
The bit is also cleared when a bit manipulation instruction is executed for any of other bit of SMBS0.
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