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參數(shù)資料
| 型號(hào)： | μPD78F9217Y |
| 廠(chǎng)商： | NEC Corp. |
| 英文描述： | 8 Bit Single Chip Microcontrollers(8 位單片微控制器) |
| 中文描述： | 8位單片機(jī)微控制器（8位單片微控制器） |
| 文件頁(yè)數(shù)： | 25/148頁(yè) |
| 文件大?。?/td> | 621K |
| 代理商： | ΜPD78F9217Y |
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Preliminary Product Information
25
μ
PD78F9217Y
Figure 6-2. Format of EEPROM Write Control Register 0
0
EWCS02 EWCS01 EWCS00
ERST0
ERE0
EWST0
EWE0
EEWC0
Symbol
Address
When reset
R/W
FFCCH
04H
R/W
6
7
0
5
4
3
2
1
EWCS02 EWCS01 EWCS00
EEPROM timer count clock selection
f
CC
/2
3
(500 kHz)
f
CC
/2
4
(250 kHz)
f
CC
/2
5
(125 kHz)
f
CC
/2
6
(62.5 kHz)
f
CC
/2
7
(31.3 kHz)
f
CC
/2
8
(15.6 kHz)
8-bit timer (TM80) output
f
XT
(32.768 kHz)
EEPROM write time
Note 2
2
3
/f
CC
×
145 (Not to be set
Note 3
)
2
4
/f
CC
×
145 (Not to be set
Note 3
)
2
5
/f
CC
×
145 (Not to be set
Note 3
)
2
6
/f
CC
×
145 (Not to be set
Note 3
)
2
7
/f
CC
×
145 (4.64 ms)
2
8
/f
CC
×
145 (Not to be set
Note 3
)
Output cycle of TM80
×
145
1/f
XT
×
145 (4.43 ms)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ERE0
EWE0
Write
Read
Remarks
EEPROM is in the standby state (low power consumption mode).
0
1
×
0
1
Disabled
Disabled
Enabled
Disabled
Enabled
Enabled
EWST0
EEPROM write status flag
Data is not being written to the EEPROM. (Data can be written to or read from the EEPROM. However,
the EEPROM cannot be written to when EWE0 = 0.)
0
1
ERST0
EEPROM read status flag
Data cannot be read from the EEPROM.
Data can be read from the EEPROM.
0
1
Note 1
Data is being written to the EEPROM. (Data cannot be written to and read from the EEPROM.)
Notes
1.
Bits 1 and 3 are read-only.
2.
Set the EEPROM write time to a value between 3.3 and 6.6 ms. The value specified for the EEPROM
write time is that value set as a target in the products development stage, and is subject to change after
evaluation. When designing your system, refer to the Data Sheet that will be prepared after evaluation.
3.
This setting is prohibited because the EEPROM write time falls outside the range of 3.3 to 6.6 ms.
Caution
ERST0 is 0 during a reset, immediately after a reset, in STOP mode, and immediately after release
of STOP mode. However, ERST0 is set to 1 when a certain oscillation settling time has elapsed.
ERST0 = 0 when ERE0 is set to 0, while EWST0 = 1, and during standby release time in the case the
value of ERE0 is changed from 0 to 1.
Remarks 1.
f
X
: Main system clock oscillation frequency
f
XT
: Subsystem clock oscillation frequency
The parenthesized values apply to operation at f
CC
= 4.0 MHz or f
XT
= 32.768 kHz.
2.
3.
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