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參數(shù)資料
| 型號： | μPD789800 |
| 廠商： | NEC Corp. |
| 英文描述： | 8 Bit Single Chip Microcontrollers(8位單片微控制器) |
| 中文描述： | 8位單片機微控制器（8位單片微控制器） |
| 文件頁數(shù)： | 20/48頁 |
| 文件大小： | 266K |
| 代理商： | ΜPD789800 |
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20
μ
PD789800
5.6
Key Return Signal Detection Circuit
The
μ
PD789800 incorporates the key return signal detection circuit that can detect the key return signals input to
the P40/KR00-P47/KR07 pins.
Specify whether to detect the key return signals at the P40/KR00-P47/KR07 pins by means of key return mode
register 00 (KRM00). Inhibit interrupts before setting KRM00 (see
Caution 3
).
KRM00 is set by a 1-bit memory operation instruction or an 8-bit memory operation instruction.
Bit 0 (KRM000) corresponds to the KR00/P40-KR03/P43 pins. Its setting is common to these four pins. Bits 4 to
7 (KRM004-KRM007) correspond to the KR04/P44-KR07/P47 pins respectively and are set bit by bit.
Inputting the RESET signal clears KRM00 to 00H.
Figure 5-8 shows the format of key return mode register 00. Figure 5-9 shows the block diagram of the falling
edge detection circuit.
Figure 5-8. Format of Key Return Mode Register 00
Symbol
7
6
5
4
3
2
1
0
Address
When reset
R/W
KRM00 KRM007
KRM006
KRM005
KRM004
0
0
0
KRM000
F F F 5 H
0 0 H
R/W
KRM00n
Selection of key return signal detection for the P4n/KR0n pin (n = 4 to 7)
0
No detection
1
Detection (detecting the falling edges of the P4n/KR0n signals)
KRM000
Selection of key return signal detection for the P40/KR00-P43/KR03 pins
0
No detection
1
Detection (detecting the falling edges of the P40/KR00-P43/KR03 signals)
Cautions 1.
Be sure to set 0 in bits 1 to 3.
When KRM00 is set to 1, the pull-up resistor is forcibly connected to the corresponding
pin. However, when the pin is placed in output mode, the pull-up resistor is
disconnected.
Before setting KRM00, inhibit interrupts (set bit 4 of interrupt mask flag register 0 (MK0)
(KRMK00 = 1). After setting KRM00, clear bit 4 of interrupt request flag register 0 (IF0)
(KRIF00 = 0), then permit interrupts (clear bit 4 of MK0 (KRMK00 = 0)).
2.
3.
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