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433
CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Check Level
Pin Output Level Check
[Instruction format]
CHKL sfr
[Operation]
(Pin level) (output latch)
[Operands]
Mnemonic
Operands
CHKL
sfr
[Flags]
S
Z
AC
P/V
CY
×
×
P
[Description]
The exclusive logical sum of the output pin level and output buffer prestage signal level is found.
The S flag is set (1) if bit 7 is set (1) as a result of the exclusive logical sum operation, and S flag is cleared
(0) if bit 7 is cleared (0).
The Z flag is set (1) if all bits are 0 as a result of the exclusive logical sum operation, and Z flag is cleared (0)
if there are non-zero bits.
The P/V flag is set (1) if the number of bits in the data set (1) as a result of the exclusive logical sum operation
is even, and cleared (0) if the number is odd.
This instruction is used to detect an abnormal state which has arisen for some reason or other in which the output
pin level and the output buffer prestage signal level are different. In normal operation, the Z flag is always set
(1).
When this instruction is executed, with a product that has a port read control register (PRDC), the PRDC0 bit
of the PRDC register must be cleared (0). An abnormal state cannot be detected if the PRDC0 bit is set (1).
When this instruction is executed on a port that includes a pin used as a control output, the input/output mode
for the port with a pin used as a control output must be set to input mode. If the input/output mode for a port
with a pin used as a control output is set to output mode, operation may be judged to be abnormal even though
it is normal.
A pin for which the input/output mode as a port is specified as the input mode will always be judged to be normal
by this instruction.
[Coding example]
CHKL P0
BNZ $ERROR ; Checks whether the port 0 pin level and output buffer prestage signal level match, and if they do
not, branches to address ERROR
Caution The CHKL instruction is not available in the
μ
PD784216, 784216Y, 784218, 784218Y, 784225,
784225Y, 784937 Subseries. Do not execute this instruction. If this instruction is executed, the
following condition will result.
After the pin levels of output pins are read two times, they are exclusive-ORed. As a result,
if the pins checked with this instruction are used in the port output mode, the exclusive-OR
result is always 0 for all bits, and the Z flag is set to (1).
CHKL