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CHAPTER 4 INTERRUPT FUNCTIONS
4.2 Interrupt Service Modes
4.2.1 Vectored interrupts
A branch is made to the service routine using the memory contents of the vector table address corresponding to
the interrupt source as the branch destination address.
The following operations are executed to enable the CPU to perform interrupt servicing.
When branching: The CPU state (PC & PSW contents) is saved to the stack.
When returning : CPU statuses (PC & PSW contents) are restored from the stack.
The return from the service routine to the main routine is performed by an RETI instruction (or an RETB instruction
in the case of a BRK instruction or operand error interrupt).
The branch destination address is restricted to the base area from 0000H to FFFFH.
Please refer to the
User’s Manual — Hardware
for the individual products for details of the vector table.
4.2.2 Context switching
The prescribed register bank is selected by hardware by generation of an interrupt request or execution of a BRKCS
RBn instruction. With this function, a branch is made to the vector address stored beforehand in the register bank,
and at the same time the contents of the program counter (PC) and program status word (PSW) are stacked in the
register bank.
The return from the service routine is performed by a RETCS !addr16 instruction (or an RETCSB !addr16 instruction
in the case of a BRKCS RBn instruction).
The branch destination address is restricted to the base area from 0000H to FFFFH.
Figure 4-1. Context Switching Operation by Interrupt Request Generation
0000B
7 Transfer
PC19-PC16
PC15-PC0
Temporary register
PSW
Save
1
Save
1
(temporary
register
bit 8 to 11)
Exchange
6
Save
5
Register bank n (n = 0 to 7)
V
U
T
W
A
X
B
C
R5
R4
R7
R6
VP
UP
D
E
H
L
Register bank
switching
(RBS0-RBS2
←
n
)
RSS
←
0
IE
←
0
3
4
Register bank
(0 to 7)