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CHAPTER 2 MEMORY SPACE
2.4 Internal Data Area
The internal data area comprises the internal RAM area and special function register area. In some products,
memories dependent on other hardware are also allocated to this areas (see the
User’s Manual — Hardware
of each
The final address of the internal data area can be specified by means of the LOCATION instruction as either FFFFH
(when a LOCATION 0 instruction is executed) or FFFFFH (when a LOCATION 0FH instruction is executed). Selection
of the addresses of the internal data area by means of the LOCATION instruction must be executed once immediately
after reset release, and once the selection is made, it cannot be changed. The program after reset release must be
as shown in the example below. If the internal data area and another area are allocated to the same addresses, the
internal data area is accessed and the other area cannot be accessed.
Example
RSTVCT
CSEG
DW
~
AT 0
RSTSTRT
INITSEG
RSTSTRT:LOCATION 0H; or LOCATION 0FH
MOVG SP, #STKBGN
CSEG
BASE
Cautions 1. When the LOCATION 0 instruction is executed, it is necessary to ensure that the program after
reset release does not overlap the internal data area. It is also necessary to make sure that
the entry addresses of the service routines for non-maskable interrupts such as NMI do not
overlap the internal data area. Also, initialization must be performed for maskable interrupt
entry areas, etc., before the internal data area is referenced.
2. The
μ
PD784915 Subseries is fixed to the LOCATION 0 instruction.
2.4.1 Internal RAM area
78K/IV Series products incorporate general-purpose static RAM.
This area is configured as follows:
Peripheral RAM (PRAM)
Internal RAM area
Internal high-speed RAM (IRAM)