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CHAPTER 6 INSTRUCTION SET
6.5 Number of Instruction Clocks
6.5.1 Execution time of instruction
The execution time for instructions is shown as the number of clocks of f
CLK
.
The CPU in the 78K/IV Series has an instruction queue, so that another instruction can be prefetched in parallel
while one instruction is executed. Consequently, the actual execution time of an instruction is dependent on the
preceding instruction.
The execution time of an instruction also changes with the number of wait states used for memory access.
Therefore, the accurate execution time of the program cannot be calculated by merely adding the number of execution
clocks of instructions.
The minimum number of execution clocks is shown for instructions except those used for branch operation, such
as BR, CALL, and RET instructions. For the branch instructions, the number of clocks slightly more than the minimum
value is shown.
6.5.2 Definitions for “Clocks” column
(1) Internal ROM
The number of clocks set to 1 if the data to be accessed by an instruction is stored in the internal ROM and
if the IFCH bit, which is bit 7 of the memory mapping mode register (MM), is shown. If the IFCH bit is cleared
to 0, refer to the column of PRAM, EMEM, or SFR.
(2) IRAM
The number of clocks if the data to be accessed by an instruction is stored in the internal high-speed RAM
(the area of addresses FD00H through FEFFH when LOCATION 0 instruction is executed, and the area of
FFD00H through FFEFFH when LOCATION 0FH instruction is executed) is shown.
The
μ
PD784915 Subseries is fixed to the LOCATION instruction.
(3) PRAM/EMEM/SFR
The number of clocks if the data to be accessed by an instruction is stored in an area of the internal RAM
which is not IRAM, in the external memory (including the external SFR), or in the SFR area is shown.
(4) Others
The number of clocks if no data is accessed by an instruction is shown.