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115
CHAPTER 3 REGISTERS
Example
The operation of the overflow flag when an 8-bit addition instruction is executed is shown below.
When the addition of 78H (+120) and 69H (+105) is performed, the operation result is E1H (+225),
and the two’s complement limit is exceeded, with the result that the P/V flag is set (1). Expressed
as a two’s complement, E1H is –31.
78H (+120)
=
0 1 1 1
1 0 0 0
+)
69H (+105)
=
+) 0 1 1 0
1 0 0 1
0
↑
1 1 1 0
0 0 0 1
=
–31
P/V = 1
CY
When the following two negative numbers are added together, the operation result is within the
two’s complement range, and therefore the P/V flag is reset.
FBH (–5)
=
1 1 1 1
1 0 1 1
+)
F0H (–16)
=
+) 1 1 1 1
0 0 0 0
1
↑
1 1 1 0
1 0 1 1
=
–21
P/V = 0
CY
(3) Interrupt request enable flag (IE)
This flag controls CPU interrupt request acknowledgment operations.
When “0”, interrupts are disabled, and only non-maskable interrupts and unmasked macro service requests
can be acknowledged. All other interrupts are disabled.
When “1”, the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled
by the interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual
interrupts.
The IE flag is set (1) by execution of an EI instruction, and reset (0) by execution of a DI instruction or
acknowledgment of an interrupt.
(4) Auxiliary carry flag (AC)
The AC flag is set (1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation,
and reset (0) otherwise.
This flag is used when the ADJBA or ADJBS instruction is executed.
(5) Register set selection flag (RSS)
The RSS flag specifies the general registers that function as X, A, C, and B, and the general register pairs
(16-bit) that function as AX and BC.
This flag is provided to maintain compatibility with the 78K/III Series, and must be set to 0 except when using
a 78K/III Series program.