μ
PD784044(A), 784046(A)
66
(2) Electrical specifications of
μ
PD784044(A1), 784046(A1) (4/6)
AC Characteristics (T
A
= –40 to +110 C, V
DD
= 4.5 to 5.5 V, V
SS
= 0 V)
Read/write operation
Parameter
Symbol
Expression
MIN.
MAX.
Unit
System clock cycle time
t
CYK
100
250
ns
Address setup time (vs. ASTB
↓
)
t
SAST
(0.5 + a) T – 20
30
ns
Address hold time (vs. ASTB
↓
)
t
HSTA
0.5T – 20
30
ns
ASTB high-level width
t
WSTH
(0.5 + a) T – 17
33
ns
Address
→
RD
↓
delay time
t
DAR
(1 + a) T – 15
85
ns
RD
↓→
address float time
t
FRA
0
ns
Address
→
data input time
t
DAID
(2.5 + a + n) T – 56
194
ns
RD
↓→
data input time
t
DRID
(1.5 + n) T – 53
97
ns
ASTB
↓→
RD
↓
delay time
t
DSTR
0.5T – 16
34
ns
Data hold time (vs. RD
↑
)
t
HRID
0
ns
RD
↑→
address active time
t
DRA
0.5T – 14
36
ns
RD low-level width
t
WRL
(1.5 + n) T – 30
120
ns
Address
→
LWR, HWR
↓
delay time
t
DAW
(1 + a) T – 15
85
ns
LWR, HWR
↓→
data output time
t
DWOD
15
ns
ASTB
↓→
LWR, HWR
↓
delay time
t
DSTW
0.5T – 16
34
ns
Data setup time (vs. LWR, HWR
↑
)
t
SODW
(1.5 + n) T – 25
125
ns
Data hold time (vs. LWR, HWR
↑
)
t
HWOD
0.5T – 14
36
ns
LWR, HWR
↑→
ASTB
↑
delay time
t
DWST
1.5T – 15
135
ns
LWR, HWR low-level width
t
WWL
(1.5 + n) T – 36
114
ns
Address
→
WAIT
↓
input time
t
DAWT
(2 + a) T – 50
150
ns
ASTB
↓→
WAIT
↓
input time
t
DSTWT
1.5T – 40
110
ns
ASTB
↓→
WAIT hold time
t
HSTWT
(1.5 + n) T + 5
155
ns
ASTB
↓→
WAIT
↑
delay time
t
DSTWTH
(1.5 + n) T – 40
210
Note
ns
RD
↓→
WAIT
↓
input time
t
DRWT
T – 40
60
ns
RD
↓→
WAIT hold time
t
HRWT
(1 + n) T + 5
105
ns
RD
↓→
WAIT
↑
delay time
t
DRWTH
(1 + n) T – 40
160
Note
ns
LWR, HWR
↓→
WAIT
↓
input time
t
DWWT
T – 40
60
ns
LWR, HWR
↓→
WAIT hold time
t
HWWT
(1 + n) T + 5
105
ns
LWR, HWR
↓→
WAIT
↑
delay time
t
DWWTH
(1 + n) T – 40
160
Note
ns
Note
Specification when an external wait is inserted
Remarks 1.
T = t
CYK
= 1/f
CLK
(f
CLK
is internal system clock frequency)
2.
a = 1 when an address wait is inserted, otherwise, 0.
3.
n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or program-
mable wait control registers 1, 2 (PWC1, PWC2). (n
≥
0. n
≥
1 for t
DSTWTH
, t
DRWTH
, t
DWWTH
).
4.
Calculate values in the expression column with the system clock cycle time to be used because
these values depend on the system clock cycle time (t
CYK
= T). The values in the above expression
column are calculated based on T = 100 ns.