![](http://datasheet.mmic.net.cn/370000/-PD784036Y_datasheet_16681079/-PD784036Y_184.png)
CHAPTER 5 PORT FUNCTIONS
146
5.8 PORT 6
With
μ
PD784038
Port 6 is an 8-bit input/output port with an output latch. P60 to P67 incorporate a software programmable pull-up resistor.
In addition to its function as a port, port 6 also has various alternate-function control signal pin functions as shown in Table
5-11. Operations as control pins are performed by the respective function operations.
When RESET is input, P60 to P67 are set as input port pins (output high-impedance state), and the output latch contents
are undefined.
With
μ
PD784031
P60 to P63 are output port pins and P66 and P67 are input/output port pins with output latch.
P64 to P67 incorporate a software programmable pull-up resistor.
In addition to the functions as port pins, these pins also have various alternate-function control signal pin functions, as
shown in Table 2-4. Operations as control pins are performed by the respective function operations.
P64 and P65 cannot be used as port pins and function only as RD and WR output pins.
When RESET is input, the level of the above pins are set as follows:
P60 to P63: Low
P64, P65:
High
P66, P67:
Input port (output high impedance)
The higher 4 bits of the contents are undefined, and the lower 4 bits are reset to 0H.
Table 5-11 Port 6 Operating Modes
Pin Name
Port Mode
Output Mode
Control Signal Input/
Operation to Operate as Control Pins
P60 to P63
Input/output ports
Note
A16 to A19 outputs
Specified by bits MM3 to MM0 of the MM in 2-bit units
P64
RD output
P65
WR output
P66
WAIT input
Specified by bits PWn1 & PWn0 (n = 0 to 7) of the PWC1 &
PWC2 or setting P66 in the input mode
HLDRQ input
Bus hold enabled by the HLDE bit of the HLDM
P67
HLDAK output
REFRQ output
Set (to 1) the RFEN bit of the RFM
Notes
1.
These pins of the
μ
PD784031 are output port pins.
2.
With the
μ
PD784031, this pin cannot be used as a port pin.
Caution
P60 to P63 of the
μ
PD784031 are in the output high-impedance state while the RESET signal is input, but
output a low level after the RESET signal has been cleared. Therefore, design the external circuit so that
the low level may be output as the initial status.
Remark
For details, refer to
CHAPTER 23 LOCAL BUS INTERFACE FUNCTION
.
With the
μ
PD784031, or when external memory extension
mode is specified by bits MM3 to MM0 of the MM