參數(shù)資料
型號(hào)： μPD70F3003
廠商： NEC Corp.
英文描述： 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器)
中文描述： 16/32位單片機(jī)微控制器（16/32位單片微控制器）
文件頁數(shù)： 132/141頁
文件大小： 374K
代理商： ΜPD70F3003
APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER)
120
Table A-1. Instruction Mnemonic (in alphabetical order) (5/7)
Instruction
Mnemonic
Operand
Format
CY
OV
S
Z
SAT
Instruction Function
SATSUBI
imm16, reg1, reg2
VI
*
*
*
*
*
Saturated subtract. Subtracts a 16-bit immediate
sign-extended to word length from the word data
of reg1, and stores the result to reg2. However,
if the result exceeds the maximum positive value,
the maximum positive value is stored to reg2; if
the result exceeds the maximum negative value,
the maximum negative value is stored to reg2.
The SAT flag is set to 1.
SATSUBR
reg1, reg2
I
*
*
*
*
*
Saturated subtract reverse. Subtracts the word
data of reg2 from the word data of reg1, and
stores the result to reg2. However, if the result
exceeds the maximum positive value, the
maximum positive value is stored to reg2; if the
result exceeds the maximum negative value, the
maximum negative value is stored to reg2. The
SAT flag is set to 1.
SETF
cccc, reg2
IX
–
–
–
–
–
Set flag condition. The reg2 is set to 1 if a
condition specified by condition code “cccc” is
satisfied; otherwise, a 0 is stored to the register.
SET1
bit#3, disp16 [reg1]
VIII
–
–
–
*
–
Bit set. First, adds a 16-bit displacement, sign-
extended to word length, to the data of reg1 to
generate a 32-bit address. The bits, specified by
the 3-bit bit field “bbb” is set at the byte data
location specified by the generated address.
SHL
reg1, reg2
IX
*
0
*
*
–
Logical left shift. Logically shifts the word data of
reg2 to the left by ‘n’ positions (0 is shifted to the
LSB side), where ‘n’ is specified by the lower 5
bits of reg1, and writes the result to reg2.
SHL
imm5, reg2
II
*
0
*
*
–
Logical left shift. Logically shifts the word data of
reg2 to the left by ‘n’ positions (0 is shifted to the
LSB side), where ‘n’ is specified by a 5-bit
immediate data, zero-extended to word length,
and writes the result to reg2.
SHR
reg1, reg2
IX
*
0
*
*
–
Logical right shift. Logically shifts the word data
of reg2 to the right by ‘n’ positions (0 is shifted to
the MSB side), where ‘n’ is specified by the lower
5 bits of reg1, and writes the result to reg2.
SHR
imm5, reg2
II
*
0
*
*
–
Logical right shift. Logically shifts the word data
of reg2 to the right by ‘n’ positions (0 is shifted to
the MSB side), where ‘n’ is specified by a 5-bit
immediate data, zero-extended to word length,
and writes the result to reg2.
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