
μ
PD30102
34
Preliminary Data Sheet
Figure 3-10. Details of xkphys Area
Address error
4G bytes
w/o TLB mapping
cacheable
Address error
4G bytes
w/o TLB mapping
cacheable
Address error
4G bytes
w/o TLB mapping
cacheable
Address error
Address error
Address error
4G bytes
w/o TLB mapping
Uncacheable
Address error
4G bytes
w/o TLB mapping
Uncacheable
Address error
4G bytes
w/o TLB mapping
Uncacheable
F
B
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0 x
0
F
B
B
0
F
0
F
0
F
0
F
0
F
0
F
0
F
1
0
0
0
0
0
0
0
0
0
0
0
8
8
0 x
0 x
0
F
B
B
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
8
7
0 x
0 x
0
F
B
B
0
F
0
F
0
F
0
F
0
F
0
F
0
F
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0 x
0 x
0
F
B
A
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0 x
0 x
0
F
A
A
0
F
0
F
0
F
0
F
0
F
0
F
0
F
1
0
0
0
0
0
0
0
0
0
0
0
8
8
0 x
0 x
0
F
A
A
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
8
7
0 x
0 x
0
F
A
A
0
F
0
F
0
F
0
F
0
F
0
F
0
F
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0 x
0 x
0
F
A
9
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0 x
0 x
0
F
9
9
0
F
0
F
0
F
0
F
0
F
0
F
0
F
1
0
0
0
0
0
0
0
0
0
0
0
8
8
0 x
0 x
0
F
9
9
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
8
7
0 x
0 x
0
F
9
9
0
F
0
F
0
F
0
F
0
F
0
F
0
F
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0 x
0 x
0
F
9
8
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0 x
0 x
0
F
8
8
0
F
0
F
0
F
0
F
0
F
0
F
0
F
1
0
0
0
0
0
0
0
0
0
0
0
8
8
0 x
0 x
0
F
8
8
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
8
7
0 x
0 x
0
F
8
8
0
F
0
F
0
F
0
F
0
F
0
F
0
F
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0 x
0 x
0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 x
4G bytes
w/o TLB mapping
cacheable
4G bytes
w/o TLB mapping
cacheable
3.6.2 Address translation
Virtual addresses are translated into physical addresses by the internal TLB (Translation Lookaside Buffer) in page
units. The TLB has a full-associative configuration and has 64 entries at the virtual address side and 32 entries at the
physical address side. The page size is variable from 1 K to 256 Kbytes.
If a TLB entry is not found, a TLB non-coincidence exception occurs in the 32-bit mode, and an XTLB non-coincidence
exception occurs in the 64-bit mode. Change the contents of the TLB in software.
The following figure outlines address translation.