
CHAPTER 16 RTC (REALTIME CLOCK UNIT)
260
16.2.3 RTCLLREG, RTCLHREG
Initialization in terms of hardware is effected only on the RTCRST* terminal.
RTCLLREG and RTCLHREG are the registers to set the cycle of RTCLong timer. By performing storing
operation on both registers of RTCLLREG and RTCLHREG (at TClock cycle), the set cycle of the
RTCLong timer is changed. Storing to either register does not effect the change in the set cycle. In this
case, set cycle maintains the former value. The write flags for these lower-order and higher-order bits
are cleared when both have become 1 or they are reset.
For example, when the "cycle" is "m," countdown is repeated as "m"
→
"m-1"
→
...
→
"2"
→
"1" (an
interrupt occurs here)
→
"m"
→
... "1."
The RTCLong timer is a 24-bit programmable counter that counts at 30
μ
s cycle (32.768 kHz), and is
used for generating up to 512 sec of periodical interrupts.
In the current implement, the RTCLong timer stops when 0 is set as the "cycle." The minimum value
that can be set is 4. Be sure to set these registers to 4 or greater value.
Figure 16-8. RTCLLREG (0x0B00 00D0)
Position
D15
D14
D13
D12
D11
D10
D9
D8
Name
RTCLPL
[15]
RTCLPL
[14]
RTCLPL
[13]
RTCLPL
[12]
RTCLPL
[11]
RTCLPL
[10]
RTCLPL
[9]
RTCLPL
[8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Position
D7
D6
D5
D4
D3
D2
D1
D0
Name
RTCLPL
[7]
RTCLPL
[6]
RTCLPL
[5]
RTCLPL
[4]
RTCLPL
[3]
RTCLPL
[2]
RTCLPL
[1]
RTCLPL
[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit position
Bit name
Function
D[15..0]
RTCLPL[15..0]
Bits 15 through 0 of RTCLong timer interrupt cycle