
CHAPTER 8 CACHE ORGANIZATION AND OPERATION
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8.5 CACHE STATE TRANSITION DIAGRAMS
The following section describes the cache state diagrams for the data and instruction caches. These
state diagrams do not cover the initial state of the system, since the initial state is system-dependent.
8.5.1 Data Cache State Transition
The following diagram illustrates the data cache state transition sequence. A load or store operation
may include one or more of the atomic read and/or write operations shown in the state diagram below,
which may cause cache state transitions.
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Read (1) indicates a read operation from memory to cache, inducing a cache state transition.
Write (1) indicates a write operation from CPU core to cache, inducing a cache state transition.
Read (2) indicates a read operation from cache to the CPU core, which induces no cache state
transition.
Write (2) indicates a write operation from CPU core to cache, which induces no cache state
transition.
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Figure 8-6. Data Cache State Diagram
CACHE op
CACHE op
Write (1)
Write (1)
CACHE op
Write-back
Read (2)
Read (2)
Write (2)
Read (1)
Invalid
Valid
Dirty
Valid
Clean
8.5.2 Instruction Cache State Transition
The following diagram illustrates the instruction cache state transition sequence.
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Read (1) indicates a read operation from memory to cache, inducing a cache state transition.
Read (2) indicates a read operation from cache to the CPU core, which induces no cache state
transition.
Figure 8-7. Instruction Cache State Diagram
Read (1)
CACHE op
Read (2)
Valid
Invalid