
CHPAPTER 10 BCU (BUS CONTROL UNIT)
188
When finishing the read to Flash memory, perform processing from "10."
10. Compare the data written to Flash memory with the original data.
If these data accord, perform processing of "11."
If these data do not accord,
When performing write again, perform processing from "1."
When ending the process, perform processing from "11."
11. Drop the write voltage of Flash memory (V
PP
), release the Flash memory mode, and end the
processing.
12. Clear the error information from the Flash memory register.
When performing write again
If the write voltage was too low, perform processing from "1."
In other cases, perform processing from "4."
When ending the process, perform processing of "11."
10.5.5 Expansion Bus Interface
Because the V
R
4101 does not support dynamic bus sizing, it is specified that only an 8-bit access is
allowed as an access to an 8-bit device.
Dynamic bus sizing is the function to change the DATA bus width dynamically in response to the sizing
request from the target device (e.g. the bus sizing using the MEMCS16 and -IOCS16 signals of the ISA
bus).
(1) Access size in each mode
Restrictions on the access to each of an 8-bit device and 16-bit device are as described below.
(a) 8-bit device mode
Table 10-15.
Table 10-16.
Restrictions on the Access to an 8-bit
Device in the 8-bit Device Mode
Restrictions on the Access to a 16-bit
Device in the 8-bit Device Mode
Access size
Read
Write
Access size
Read
Write
Odd-numbered bytes
A
A
Odd-numbered bytes
N/A
N/A
Even-numbered
bytes
A
A
Even-numbered
bytes
A
A
2 bytes
N/A
N/A
2 bytes
A
A
4 bytes
N/A
N/A
4 bytes
A
A
8 bytes
N/A
N/A
8 bytes
A
A
16 bytes
N/A
N/A
16 bytes
A
A