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| 型號： | ZPSD612(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數(shù)： | 18/98頁 |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD612(V)E1 |
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ZPSD6XX(V) Family
12-18
ECSPLD Output
Port A, B, or D Assignments
ECS0
ECS1
ECS2
ECS3
ECS4
ECS5
ECS6
PA0, PB0
PA1, PB1
PA2, PB2
PA3, PB3
PD0*
PD1*
PD2*
Table 9. ECSPLD Output Port Assignments
The seven ECSPLD outputs may be driven off the device through Ports A, B, or D, as
shown in Table 9, via the Micro
Cell Allocator. Port selection is specified in the PSDabel
file or assigned by the PSDcompiler.
ZPLDs
(cont.)
*
Port D has no output enable (.oe) product terms for ECS4-6 outputs.
External Chip Select PLD
The External Chip Select PLD (ECSPLD) provides the means to select external devices.
The output buffer of the ECSPLD can be configured to operate in high slew rate by writing a
“1” to the corresponding bit in the Drive Register. The slew rate is a measurement of the
rise and fall times of the output. A higher slew rate means a faster output response while a
lower slew rate is a slower response. Refer to Table 25 in the I/O Section for setting up the
Drive Register.
Faster transitions are more likely to cause line reflections and system noise than slower
rates. Adjusting the slew rate allows a trade-off between greater speed and noise
sensitivity. The selection should be based on the performance requirements of the system
and its noise characteristics. Set the corresponding bits in the Drive Register to “0” (for
normal speed) or “1” (for fast drive). The default value is zero.
The ECSPLD has 24 inputs as shown in Table 8. Its outputs are combinatorial, of either
polarity, and have one product term each as shown in Figure 6.
Input Source
Input Name
Number of Bits
MCU Address Bus
A[15:0]*
16
MCU Control Signals
CNTL[2:0]
3
Power Down Signal
PDN**
1
Page Register
PGR[3:0]
4
Table 8. ECSPLD Inputs
*
*
In 80C51XA mode, the address inputs are A[19:4]
**
APD output. When PDN is high, the PSD6XX(V) is in power down mode
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