參數(shù)資料
型號： ZPSD513B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備（可編程邏輯，零功耗，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 96/142頁
文件大?。?/td> 786K
代理商： ZPSD513B1
ZPSD5XX Famly
7-96
General Description
The ZPSD5XX includes logic for sensing, masking, priority decoding and identifying up to
eight internal interrupts. The ZPSD5XX interrupt controller can generate interrupts from two
dedicated PPLD product terms, two PPLD Macrocell outputs and four terminal-count
outputs of the Counter/Timer unit.
The four interrupts generated by the PPLD can be user defined using the WSI PSDsoft
Windows compatible PC based software. Figure 46 details the basic building blocks
of the ZPSD5XX Interrupt Controller and Figure 47 shows its interface with other sections of
the ZPSD5XX.
Interrupt
Controller
Features
The ZPSD5XX interrupt controller has the following features:
J
Can accept eight interrupt inputs
J
PPLD product terms, PPLD Macrocell outputs and Terminal Counts (TCs) of
Counter/Timers can cause interrupts.
J
Interrupts generated from the PPLD can be user defined.
J
All interrupt inputs are priority decoded, IR7 has highest priority and IR0 the
lowest priority.
J
Each interrupt can be configured as either EDGE or LEVEL sensitive using the
EDGE/LEVEL register.
J
Each interrupt can be individually masked using a mask register.
J
At RESET all interrupts are MASKED.
J
Interrupt Request Latch provides the status of all interrupts.
J
Reading an Interrupt vector location clears the corresponding pending interrupt.
J
Any of these interrupts trigger a GLOBAL interrupt output available as an output at port
E (PE2) and/or as an input to the PPLD.
Interrupt Operation
On RESET all Registers and Latches are cleared and all interrupts are masked. During
initialization of the interrupt controller, relevant interrupts are un-masked and defined
whether EDGE or LEVEL sensitive. When one or more interrupts are raised high,
the “interrupt request latch” latches in all the non-masked interrupts. A 3-bit priority encoder
assigns the priority to the non-masked pending interrupts. The MCU (microcontroller)
can clear the Edge-sensitive pending interrupts by reading the “Interrupt Read Clear
Register”. Level-sensitive interrupts continue to be pending even after the MCU reads the
“Interrupt Read Clear Register”. The MCU would typically service each interrupt in
sequence according to priority. Refer to Table 28 regarding priorities of various interrupts.
Any of these interrupts trigger a GLOBAL interrupt output available as an input to the PPLD
(INTR2PLD) and as output at port E (PE2). Refer to Figures 46 and 47 for details of the
interrupt architecture.
Interrupt
IR 7
IR 6
IR 5
IR 4
IR 3
IR 2
IR 1
IR 0
Priority
HIGHEST
^
^
^
^
^
^
LOWEST
Table 28. Interrupt Priority Table
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
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