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| 型號(hào)： | ZPSD513B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入） |
| 文件頁(yè)數(shù)： | 4/142頁(yè) |
| 文件大小： | 786K |
| 代理商： | ZPSD513B1 |
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ZPSD5XX Famly
7-4
The ZPSD5XX series of Field Programmable Microcontroller Peripherals represent a major
advance in the evolution of Programmable Peripherals. They combine an innovative
architecture with state of the art technology to provide user programmability (logic,
functions, memory), flexibility, high integration, optimum performance, low power . For
example, the PSD513B1 can implement a full peripheral subsystem and has the following
features:
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Three ZPLDs with a total of 61 inputs, 140 product terms outputs, 30 macrocells and
24 I/O pins.
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40 individually programmable I/O pins that are divided into 5 Ports.
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Four 16-bit Peripheral PLD (PPLD)-controlled Counter/Timers that can perform pulse,
waveform, time capture, event counting and watch dog functions.
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Eight input priority encoded Interrupt Controller. Four interrupts are generated by the
Counter/Timer unit and the other four can be user defined through the PPLD.
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4-Bit Page Register
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1 Mbit Reprogrammable EPROM consists of four 256 Kbit blocks.
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16 Kbit of standby SRAM that can automatically switch into standby mode.
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Power management unit with automatic standby and sleep modes.
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Security mode.
Figure 2 is a top level block diagram of the ZPSD5XX. Refer to Table 1 and other sections
for details on functionality, DC/AC specification, packages and ordering information.
At the core of the ZPSD5XX are dedicated ZPLDs based on the functions they perform:
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Decoding ZPLD (DPLD)
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General Purpose ZPLD (GPLD)
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Peripheral ZPLD (PPLD)
All ZPLDs receive the same inputs through the ZPLD bus and are differentiated by their
output destinations. The Decoder PLD (DPLD ) has as its main function to perform address
space decoding for the internal I/O Ports, Peripherals, four blocks of EPROM, standby
SRAM and peripheral mode of Port A. The address decoding can be based on any address
input, control signal (RD, PSEN, etc.) and page logic. Address inputs originate from either
the microcontroller interface (ADIO Port) or other I/O Ports for additional decoding. The
DPLD also supports special requirements of 8031 architecture based designs that need to
store data in the EPROM or execute programs from the SRAM.
The general purpose PLD (GPLD) is a general purpose ZPLD that can be used to
implement state machines and logic . The GPLD has up to 61 inputs, 118 product terms,
24 flexible macrocells and 24 I/O pins that are connected to Ports A, B and E. The GPLD
can also decode the microcontroller address bus and generate chip selects to external
peripherals or memories.
General
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZPSD513B1V | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| ZPSD501B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| ZPSD501B1V | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| ZPSD503B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| ZPSD503B1V | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD513B1-C-15L | 制造商:WSI 功能描述: |
| ZPSD602E1-15L | 制造商:WSI 功能描述: |
| ZPSD611E1-15J | 制造商:WSI 功能描述: |
| ZPSD611E1-15JI | 制造商:WSI 功能描述: |
| ZPSD611E1-15L | 制造商:WSI 功能描述: |
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