參數(shù)資料
型號(hào)： ZPSD401A2
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入）
文件頁數(shù)： 71/108頁
文件大小： 626K
代理商： ZPSD401A2
ZPSD4XX Famly
5-71
Power
Management
Unit
(Cont.)
Oher Power Saving Options
The ZPSD4XX provides additional power saving options. These options, except the SRAM
Standby Mode, can be enabled/disabled by setting up the corresponding bit in the PMMR.
J
EPROM
The EPROM power consumption in the PSD is controlled by bit 3 in the
PMMR0 – EPROM CMiser. Upon reset the CMiser bit is OFF. This will cause the
EPROM to be ON at all times as long as CSI is enabled (low). The reason this mode is
provided is to reduce the access time of the EPROM by 10 ns relative to the low power
condition when CMiser is ON. If CSI is disabled (high) the EPROM will be deselected
and will enter standby mode (OFF) overriding the state of the CMiser.
If CMiser is set (ON) then the EPROM will enter the standby mode when not selected.
This condition can take place when CSI is high or when CSI is low and the EPROM is
not accessed. For example, if the MCU is accessing the SRAM, the EPROM will be
deselected and will be in low power mode.
An additional advantage of the CMiser is achieved when the PSD is configured in the
by 8 mode (8 bit data bus). In this case an additional power savings is achieved in the
EPROM (and also in the SRAM) by turning off 1/2 of the array even when the EPROM
is accessed (the array is divided internally into odd and even arrays).
The power consumption for the different EPROM modes is given in the DC
Characteristics table under I
CC
(DC) EPROM Adder.
J
SRAM Standby Mode
The SRAM has a dedicated supply voltage V
STBY
that can be used to connect a battery.
When V
CC
becomes lower than V
STBY
–0.6 then the ZPSD4XX will automatically
connect the V
STBY
as a power source to the SRAM. The SRAM Standby Current (I
STBY
)
is typically 0.5 μA.
SRAM data retention voltage V
DF
is 2 V minimum.
J
Zero Power ZPLD
ZPLD power/speed is controlled by the ZPLD_Turbo bit (bit 4) in the PMMR0.
After reset the ZPLD is in Turbo mode and runs at full power and speed. By setting the
bit to “1”, the Turbo mode is disabled and the ZPLD is consuming Zero Power current if
the inputs are not switching for an extended time of 70 ns. The propagation delay time
will be increased by 10ns after the Turbo bit is set to “1” (turned off) if the inputs change
at a frequency of less than 15 MHz.
See page 5-108
for CMiser Errata.
相關(guān)PDF資料
PDF描述
ZPSD403A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
ZPSD403A2 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
ZPSD412A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
ZPSD412A2 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
ZPSD402A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD401A2-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD401A2-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD401A2-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD401A2-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD401A2-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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