參數(shù)資料
型號(hào)： ZPSD401A2
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入）
文件頁數(shù)： 1/108頁
文件大?。?/td> 626K
代理商： ZPSD401A2
5-1
Key Features
Programmable Peripheral
ZPSD4XX Famly
Field-Programmable Microcontroller Peripherals
J
Complete family of Field Programmable Microcontroller Peripherals enables the
user to efficiently implement a highly integrated embedded control system in a short
time. The ZPSD4XX family has a variety of functions such as ZPLDs , I/O Ports, Power
Management, EPROM and SRAM.
J
“No Glue-Logic” user programmable interface to 8 or 16 bit microcontroller multiplexed
and non-multiplexed bus. The bus control logic can directly decode control signals
generated by 8031, 80196, 80186, 68HC11, 68HC16, 683XX, 16000, Z80, and Z8
architecture. Extended address capability up to 24 bits of address.
J
A range of ZPLD (Zero Power PLD) architectures have up to 24 macrocells, 59 inputs
and 126 output product terms. The ZPSD4XX includes 2 functional ZPLDs which enable
the user to efficiently implement a variety of state machines, logic functions, address
decoding and control of the internal ZPSD4XX functional blocks .
J
The ZPLDs use a Zero Power CMOS technology that reduces the device standby
current to 5 uA typical. Unused product terms are disabled to reduce operating power.
J
40 I/O Ports that can be individually configured by the user as standard MCU I/O ports,
PLD I/O, latched address outputs and special function I/O. Two eight bit I/O ports can
be configured as Open Drain Outputs.
J
The ZPSD4XX family contains EPROM densities of 256 Kbit, 512 Kbit and 1 Mbit that
can be configured as 8 or 16 bit data width. The EPROM is divided into 4 equal blocks
that can be mapped to different address spaces. Access time is 70 ns which includes
address latching and decoding PLD. The EPROM has a low power mode that is
controlled by the CMiser-Bit.
J
The ZPSD4XX family contains a 16 Kbit scratch pad SRAM that can be configured
as 8 or 16 bit data width. Access time is 70 ns which includes address latching and
decoding PLD. The SRAM can be used as standby storage if standby power is supplied
to the Vstdby pin. Switching between V
CC
and Vstdby occurs automatically.
J
Page Logic is connected to the ZPLDs and enables address space expansion of
Microcontrollers with limited address space capability. Up to 16 pages are available.
J
A security bit prevents reading the ZPSD4XX configuration, ZPLD and EPROM
contents. This inhibits copying the device on a programmer.
J
Port A can be used as a buffered microcontroller data bus ( Peripheral I/O Mode) of the
microcontroller bus. This provides easy access to sub-systems that require more drive
on the data bus or accessing a resource that is shared by another MCU or DMA
Controller.
相關(guān)PDF資料
PDF描述
ZPSD403A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
ZPSD403A2 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
ZPSD412A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
ZPSD412A2 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
ZPSD402A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD401A2-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD401A2-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD401A2-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD401A2-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD401A2-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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