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| 型號： | ZPSD304RV |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個可編程I/O,通用PLD有16個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，無的SRAM，19余個可編程輸入/輸出，通用PLD的有16個輸入） |
| 文件頁數(shù)： | 13/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | ZPSD304RV |
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ZPSD3XX Famly
3-13
Zero Power
Programmable
Address
Decoder (PAD)
The ZPSD3XX consists of two zero power programmable arrays referred to as PAD A and
PAD B (Figure 4). PAD A is used to generate chip select signals derived from the input
address to the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals. All its I/O
functions are listed in Table 3 and shown in Figure 4. PAD B outputs to Ports B and C for off-
chip usage.
PAD B can also be used to extend the decoding to select external devices or as a random
logic replacement. The input bus to both PAD A and PAD B is the same. Using WSI’s
development software, each programmable bit in the PAD’s array can have one of three
logic states of 0, 1, and don’t care (X). In a user’s logic design, both PADs can share the
same inputs using the X for input signals that are not supposed to affect other functions.
The PADs use reprogrammable CMOS EPROM technology and can be programmed and
erased by the user.
Multiplexed Address/Data
Non-Multiplexed Address/Data
8-bit Data Bus
I/O or low-order address
lines or Low-order multiplexed
address/data byte
Port A
D0–D7 data bus byte
Port B
I/O and/or CS0–CS7
I/O and/or CS0–CS7
AD0/A0–AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
AD8/A8–AD15/A15
High-order address
bus byte
High-order address bus byte
16-bit Data Bus
I/O or low-order address
lines or low-order multiplexed
address/data byte
Port A
Low-order data bus byte
Port B
I/O and/or CS0–CS7
High-order data bus byte
AD0/A0–AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
AD8/A8–AD15/A15
High-order multiplexed
address/data byte
High-order address bus byte
Table 2.
ZPSD30X Bus
and Port
Configuration
Options
Multiplexed Address/Data
Non-Multiplexed Address/Data
8-bit Data Bus
I/O or low-order address
lines or low-order multiplexed
address/data byte
Port A
D0–D7 data bus byte
Port B
I/O and/or CS0–CS7
I/O and/or CS0–CS7
AD0/A0–AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
A8–A15
High-order address bus byte
High-order address bus byte
Table 2a.
ZPSD31X Bus
and Port
Configuration
Options
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| ZPSD311 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PSD3XX/ZPSD3XX FAMILY LOW COST MICROCONTROLLER PERIPHERALS |
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| ZPSD311-15LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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