參數(shù)資料
型號(hào)： ZPSD302V
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有16個(gè)輸入）
文件頁數(shù)： 15/90頁
文件大小： 491K
代理商： ZPSD302V
ZPSD3XX Famly
3-15
Function
PADA and PADB Inputs
In CSI mode (when high), PAD deselects all of its outputs and enters a
power-down mode (see Tables 12 and 13). In A19 mode, it is another
input to the PAD.
These are general purpose inputs from Port C. See Figure 4, Note 6.
These are address inputs.
These are page number inputs
(not available on ZPSD3X1 versions).
This is the read pulse or enable strobe input. (Note 9)
This is the write pulse or R/W select signal.
This is the ALE input to the chip.
This deselects all outputs from the PAD; it can not be used in product
term equations. See Tables 10 and 11.
A19/CSI
A16–A18
A11–A15
P0–P3
RD/E/DS
WR or R/W
ALE
RESET
PADA Outputs
These are internal chip-selects to the 8 EPROM banks. Each bank can
be located on any boundary that is a function of one product term of the
PAD address inputs.
This is an internal chip-select to the SRAM. Its base address location is
a function of one term of the PAD address inputs.
This internal chip-select selects the I/O ports. It can be placed on any
boundary that is a function of one product term of the PAD inputs. See
Tables 6 and 7.
This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the input
direction of Port A. CSADIN is gated externally to the PAD by the
internal read signal. When CSADIN and a read operation are active, data
presented on Port A flows out of AD0/A0–AD7/A7. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 6.
This internal chip-select, when Port A is configured as a low-order
address/data bus in track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT1 is gated externally to the PAD by the
ALE signal. When CSADOUT1 and the ALE signal are active, the
address presented on AD0/A0–AD7/A7 flows out of Port A.
This chip-select can be placed on any boundary that is a function of one
product term of the PAD inputs. See Figure 6.
This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT2 must include the write-cycle control
signals as part of its product term. When CSADOUT2 is active, the data
presented on AD0/A0–AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 6.
ES0–ES7
RS0
CSIOPORT
CSADIN
CSADOUT1
CSADOUT2
PAD B Outputs
CS0–CS3
These chip-select outputs can be routed through Port B. Each of them is
a function of up to four product terms of the PAD inputs.
These chip-select outputs can be routed through Port B. Each of them is
a function of up to two product terms of the PAD inputs.
These chip-select outputs can be routed through Port C. See Figure 4,
Note 6. Each of them is a function of one product term of the PAD inputs.
CS4–CS7
CS8–CS10
Table 3.
ZPSD3XX
PADA and PAD
B Functions
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