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參數(shù)資料
| 型號(hào)： | Z9953AA |
| 英文描述： | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):20A; Peak Non Repetitive Surge Current, Itsm:300A; Gate Trigger Current Max, Igt:30uA |
| 中文描述： | 八分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 32腳|塑料 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 43K |
| 代理商： | Z9953AA |
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07086 Rev. *A
06/18/2001
Page 3 of 6
Z9953
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
Maximum Input Current:
-65
°
C to + 150
°
C
-40
°
C to +85
°
C
2KV
5.5V
±
20mA
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Output Low Voltage
Output High Voltage
Symbol
VIL
VIH
IIL
IIH
VPP
Min
VSS
2.0
Typ
Max
Units
V
V
μA
μA
mV
Conditions
-
-
0.8
VDD
-120
120
1000
Note 1
300
Note 2
VCMR
VDD-
1.5
-
VDD-
0.6
0.6
V
VOL
VOH
V
V
IOL = 20mA, Note 3
IOH = -20mA, Note 3
VDD-
0.6
-
-
-
Quiescent Supply Current
PLL Supply Current
Input Capacitance
IDDC
IDD
Cin
-
20
20
4
mA
mA
pF
All VDDC and VDD
VDD only
15
-
VDD = VDDC = 3.3V
±
5%, TA = -40
°
C to +85
°
C
Note 1:
Inputs have pull-up, pull-down resistors that affect input current.
Note 2:
The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when
the “High” input is within the VCMR range and the input lies within the VPP specification.
Note 3:
Driving series or parallel terminated 50
(or 50
to VDD/2) transmission lines. Output buffers are dual staged to control
drive strength in order to reduce over/under shoot.
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