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參數(shù)資料
| 型號： | Z9305DZ |
| 英文描述： | FIVE DISTRIBUTED-OUTPUT CLOCK DRIVER|SOP|8PIN|PLASTIC |
| 中文描述： | 五分布式輸出時(shí)鐘驅(qū)動器|?？苵 8引腳|塑料 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 134K |
| 代理商： | Z9305DZ |
Z9305/Z9309
Document #: 38-07196 Rev. **
Page 2 of 7
Product Description
The Z9309 is a low cost 3.3V zero delay buffer designed to
distribute high speed clocks in PC system devices and
SDRAM modules and is available in a 16-pin SOIC or TSSOP
package. The Z9305 is an 8-pin version of the Z9309 and it
accepts one reference input and drives out five low skew
clocks. The devices have an on-chip PLL which locks to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
The Z9309 has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the Table 1. If all
output clocks are not required, Bank B can be tri-stated. The
select inputs also allow the input clock to be directly applied to
the output for chip and system testing purposes.
The Z9305 and Z9309 PLLs enter a Power Down mode when
there are no rising edges on the REF input. In this state, the
outputs are tri-stated and the PLL is turned off, resulting in less
than 50 uA of current draw. The Z9309 PLL shuts down in one
additional case as shown in Table 1.
Multiple Z9305 and Z9309 devices can accept the same input
clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter. The input
to output propagation delay is guaranteed to be less than 350
ps, and the output to output skew is guaranteed to be less than
250 ps.
Connection Diagram
CLKOU
CLK4
VDD
CLK3
1
2
3
4
8
7
6
5
REF
CLK2
CLK1
GND
Z
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
LKA1
LKA2
VDD
GND
LKB1
LKB2
S2
Z
Pin Description (Z9305)
PIN No.
1
2
3
4
5
6
7
8
Pin Name
REF
[1]
CLK2
[1]
CLK1
[1]
GND
CLK3
[1]
V
DD
CLK4
[1]
CLKOUT
[1]
I/O
I
O
O
I
O
Description
Input reference frequency, 5.0 V tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
O
O
Pin Description (9309)
PIN No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
[1]
CLKA1
[1]
CLKA2
[1]
V
DD
GND
CLKB1
[1]
CLKB2
[1]
S2
[2]
S1
[2]
CLKB3
[1]
CLKB4
[1]
GND
V
DD
CLKA3
[1]
CLKA4
[1]
CLKOUT
[1]
I/O
I
O
O
I
I
O
O
I
I
O
O
Description
Input reference frequency, 5.0 V tolerant input
Clock output, bank A
Clock output, bank A
3.3V supply
Ground
Clock output, bank B
Clock output, bank B
Select input pin, bit 2
Select input pin, bit 1
Clock output, bank B
Clock output, bank B
Ground
3.3V supply
Clock output, bank A
Clock output, bank A
O
O
O
Buffered output, internal feedback on this pin.
Notes:
1.
2.
Includes weak pull-down.
Includes weak pull-up.
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