參數(shù)資料
型號： Z9025900ZEM
英文描述： SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:600V; On-State RMS Current, IT(rms):35A; Peak Non Repetitive Surge Current, Itsm:500A; Gate Trigger Current Max, Igt:40uA
中文描述： 消費(fèi)性IC
文件頁數(shù)： 7/30頁
文件大?。?/td> 938K
代理商： Z9025900ZEM
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
PS001300-TVC1099
Preliminary
7
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Z90255 Production Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . 14
Single-Purpose Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register File Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
OSD Control Register 00H:Bank A (OSD_CNTL) . . . . . . . . . . . . . . . . . 23
Vertical Position Register 01H:Bank A (VERT_POS) . . . . . . . . . . . . . . 25
Horizontal Position Register 02H:Bank A (HOR_POS) . . . . . . . . . . . . . 26
Second Color Control Register 07H:Bank A (SNDCLR_CNTRL) . . . . . 27
Second Color Register 08H:Bank A (SNDCLR) . . . . . . . . . . . . . . . . . . 28
Mesh Column Start Register 04H: Bank F (MC_St) . . . . . . . . . . . . . . . 30
Mesh Column End Register 05H: Bank F (MC_End) . . . . . . . . . . . . . . 31
Mesh Row Enable Register 06H: Bank F (MR_En) . . . . . . . . . . . . . . . . 31
Mesh Control Register 07H: Bank F (MC_Reg) . . . . . . . . . . . . . . . . . . 32
BGR Mesh Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Fade Position Register 1 05H: Bank A (FADE_POS1) . . . . . . . . . . . . . 36
Fade Position Register 2 06H: Bank A (FADE_POS2) . . . . . . . . . . . . . 36
Row Space Register 04H: BankA (ROW_SPACE) . . . . . . . . . . . . . . . . . 37
RGB Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Display Attribute Register 03H: Bank A (DISP_ATTR) . . . . . . . . . . . . . 42
VRAM Structure and Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Color Palette Selection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Color Index Register 09H: Bank C (CLR_IDX) . . . . . . . . . . . . . . . . . . . . 46
Color Palette 0 Register 09H: Bank A (CLR_P0) . . . . . . . . . . . . . . . . . . 47
Color Palette 1 Register 0AH: Bank A (CLR_P1) . . . . . . . . . . . . . . . . . . 47
Color Palette 2 Register 0BH: Bank A (CLR_P2) . . . . . . . . . . . . . . . . . . 48
Color Palette 3 Register 0CH: Bank A (CLR_P3) . . . . . . . . . . . . . . . . . . 48
Color Palette 4 Register 0DH: Bank A (CLR_P4) . . . . . . . . . . . . . . . . . . 49
Color Palette 5 Register 0EH: Bank A (CLR_P5) . . . . . . . . . . . . . . . . . . 49
Color Palette 6 Register 0FH: Bank A (CLR_P6) . . . . . . . . . . . . . . . . . . 49
Row Attribute Register (ROW_ATTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
HV Interrupt Status Register 07H: Bank C (INT_ST) . . . . . . . . . . . . . . 51
Master I
C Control Register 0CH: Bank C (I
Master I
C Command Register 0BH: Bank C (I
Master I
C Data Register 0AH: Bank C (I
Master I
C Bus Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2
2
C_CNTL) . . . . . . . . . . . . . 55
2
C_CMD) . . . . . . . . . . . 56
C_DATA) . . . . . . . . . . . . . . . 56
2
2
2
2
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