XRT94L33
xr
Rev.1.2.0.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
284
Figure 53) is “dashed” because controlling this signal is not necessary if the user has executed “STEP 1” above.
Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for 40 periods of “TxPOHClk_n” to
elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g.,
the most significant bit) of the “outbound” H4 byte onto the “TxPOH_n” input pin, upon the very next falling
edge of “TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit SONET POH Processor”
block circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
This “WAIT STATE” period is necessary because the H4 byte is the sixth byte within the POH.
Afterwards, the “external circuit” should serially place the remaining seven bits (of the H4 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
2.2.8.3.8
SUPPORT/HANDLING OF THE Z3 BYTE
The Transmit SONET POH Processor block permits the user to control the value of the H4 byte by either of
the following options.
Setting and controlling the “outbound” Z3 Byte via Software
Setting and controlling the “outbound” Z3 Byte via the “TxPOH Input Port”
The details and instructions for using either or these features are presented below.
2.2.8.3.8.1
Setting and Controlling the Outbound Z3 Byte via Software
The Transmit SONET POH Processor block permits the user to specify the contents of the Z3 byte, within the
“outbound” STS-1 SPE via software command.
The user can configure the Transmit SONET POH Processor block to accomplish this by performing the
following steps.
STEP 1 – Write the value “0” into Bit 1 (Z3 Insertion Type) within the “Transmit SONET Path – SONET
Control Register – Byte 1”, as depicted below.
Transmit SONET Path – SONET Control Register – Byte 1 (Address = 0xN982)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Z5 Insertion
Type
Z4 Insertion
Type
Z3 Insertion
Type
H4 Insertion
Type
R/O
R/W
0
This step configures the Transmit SONET POH Processor block to read out the contents of the “Transmit
SONET Path – Transmit Z3 Byte Value” register; and load this value into the Z3 byte position within each
“outbound” STS-1 SPE.
STEP 2 – Write the desired byte value (for the outbound Z3 byte) into the “Transmit SONET Path –
Transmit Z3 Byte Value” register.
The bit-format of this register is presented below.
Transmit SONET Path – Transmit Z3 Byte Value Register (Address = 0xN9AB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_Z3_Byte_Value[7:0]