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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
227
2.2.7.3.3
TRANSMISSION OF THE REI-P INDICATOR
The Transmit STS-3c POH Processor block can be configured to transmit the REI-P indicator either (1)
automatically, (2) upon software command or (3) via the “TxPOH_n” input port as described below.
2.2.7.3.3.1
Configuring the Transmit STS-3c POH Processor block to automatically transmit the
REI-P indicator
The user can configure the Transmit STS-3c POH Processor block to automatically transmit the REI-P
indicator whenever the corresponding Receive STS-3c POH Processor block detects at least one B3 byte
error within its incoming STS-3c SPE data-stream.
The user can configure the Transmit STS-3c POH Processor block to automatically transmit the REI-P
indicator, in response to detection of B3 byte errors, by executing the following steps.
STEP 1 – Write the value [0, 0] into Bits 5 and 6 (REI-P Insertion Type[1, 0]) within the “Transmit STS-
3c Path – SONET Control Register – Byte 0” as depicted below.
Transmit STS-3c Path – SONET Control Register – Byte 0 (Address = 0x1983)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
F2 Insertion
Type
REI-P Insertion Type[1:0]
RDI-P Insertion Type[1:0]
C2 Byte
Insertion
Type
C2 Byte
Auto Insert
Mode
Enable
Transmit
AIS-P
Enable
R/W
0
This step configures the “Transmit STS-3c POH Processor” block to automatically set bits 1 through 4 (of the
G1 byte) within the “outbound” STS-3c SPE to the appropriate REI-P value, based upon receive conditions as
detected by the corresponding Receive STS-3c POH Processor block.
STEP 2 – Indicate whether the REI-P value (transmitted to the remote PTE) reflects the number of bits
(within the B3 byte) that are in error, or the number of erred STS-3c SPE that have been detected by
the corresponding Receive STS-3c POH Processor block.
The XRT94L33 permits the user to (1) flag B3 byte errors, and (2) to transmit the resulting REI-P value (back
out to the remote PTE) by the following means.
By flagging and reporting the number of bits (within the B3 byte) that have be determined to be in error,
within a given STS-3c SPE.
By flagging and reporting whether or not the corresponding Receive STS-3c POH Processor block is
currently receiving erred STS-3c SPE.
The user can choose between these two options by writing the appropriate value into Bit 0 (B3 Error Type)
within the Receive STS-3c Path – Control Register – Byte 0”; as illustrated below.
Receive STS-3c Path – Control Register – Byte 0 (Address = 0x1183)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Check
Stuff
RDI-P
Type
REI-P
Error Type
B3 Error
Type
R/O
R/W
0
X