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XRT83VSH316
87
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 62: SYSTEM SIDE TEST PATTERN SELECT REGISTER 0XN13H BIT DESCRIPTION
SYSTEM SIDE TEST PATTERN SELECT REGISTER (0XN13H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
SQRSS/
SPRBS
System QRSS/PRBS Select Bits
These bits are used to select between QRSS and PRBS for the
system side interface.
0 = PRBS
1 = QRSS
R/W
0
D6
D5
RxTEST1
RxTEST0
Receive System Side Test Code Pattern
RxTEST[2:0] are used to select a diagnostic test pattern to the sys-
tem side (receive outputs). If these bits are selected, the LIU is
automatically placed in single rail mode.
00 = RTip/Rring
01 = Rx SAIS
10 = Rx SLOS (All Zeros)
11 = Rx SQRSS/SPRBS
R/W
0
D4
D3
D2
ALARM2
ALARM1
ALARM0
Alarm Report Output (Pin RNEG, SR mode Only)
These bits are used to select which alram will be reported to the
RNEG pin in single rail mode.
000 = LCV/EXZ
001 = Line AIS
010 = Line QRPD
011 = Line RLOS
100 = System SAIS
101 = System SQRPD/SPRPD
110 = System SLOS
111 = GND
R/W
0
D1
SINVPRBS System Invert PRBS/QRSS
This bit is used to select between a normal test pattern or inverted
test pattern whenever the PRBS/QRSS is selected.
0 = Normal
1 = Inverted PRBS/QRSS
D0
SINSBER
System Insert Bit Error
When this bit transitions from a "0" to a "1", a bit error will be
inserted in the Received QRSS/PRBS pattern. The state of this bit
will be updated on the rising edge of RCLK. To ensure proper
operation, it is recommended to write a "0" to this bit before writing
a "1".
R/W
0