參數(shù)資料
型號: XRT83VSH316IB-F
廠商: Exar Corporation
文件頁數(shù): 29/98頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 16CH 316STBGA
標準包裝: 60
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: T1,E1,J1
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 316-LBGA
供應(yīng)商設(shè)備封裝: 316-STBGA(21x21)
包裝: 托盤
其它名稱: 1016-1483
XRT83VSH316IB-F-ND
XRT83VSH316
32
REV. 1.0.1
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
4.2
HDB3/B8ZS Encoder
In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3/B8ZS data. In E1 mode and
HDB3 encoding selected, any sequence with four or more consecutive zeros in the input will be replaced with
000V or B00V, where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating
the rule. An example of HDB3 encoding is shown in Table 7. In T1 mode and B8ZS encoding selected, an
input data sequence with eight or more consecutive zeros will be replaced using the B8ZS encoding rule. An
example with Bipolar with 8 Zero Substitution is shown in Table 8.
4.3
Jitter Attenuator (If enabled in the Transmit Path)
The XRT83VSH316 LIU is ideal for multiplexer or mapper applications where the network data crosses
multiple timing domains. As the higher data rates are de-multiplexed down into T1 or E1 data, stuffing bits are
typically removed which can leave gaps in the incoming data stream. The transmit jitter attenuator can be
enabled with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady T1 or E1 output.
The maximum gap width of the 16-Channel LIU is shown in Table 9.
NOTE: If the LIU is used in a loop timing system, the jitter attenuator can be placed in the receive path. See the Receive
Section of this datasheet.
TABLE 7: EXAMPLES OF HDB3 ENCODING
NUMBER OF PULSES BEFORE
NEXT 4 ZEROS
Input
0000
HDB3 (Case 1)
Odd
000V
HDB3 (Case 2)
Even
B00V
TABLE 8: EXAMPLES OF B8ZS ENCODING
CASE
PRECEDING PULSE
NEXT 8 BITS
Case 1
Input
+
00000000
B8ZS
000VB0VB
AMI Output
+
000+-0-+
Case 2
Input
-
00000000
B8ZS
000VB0VB
AMI Output
-
000-+0+-
TABLE 9: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS
FIFO DEPTH
MAXIMUM GAP WIDTH
32-Bit
20 UI
64-Bit
50 UI
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