參數(shù)資料
型號: XRT83L38IB-F
廠商: Exar Corporation
文件頁數(shù): 9/87頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83L38
14
REV. 1.0.2
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JITTER ATTENUATOR
CLOCK SYNTHESIZER
SIGNAL
NAME
LEAD #
TYPE
DESCRIPTION
JASEL0
JASEL1
A14
B13
I
Jitter Attenuator Select Pins Hardware Mode
Jitter Attenuator select Bit 0
Jitter Attenuator select Bit 1
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive
path or to disable it.
NOTE: These pins are internally pulled “Low” with 50k
Ω resistors.
SIGNAL
NAME
LEAD #
TYPE
DESCRIPTION
MCLKOUT
H1
O
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1 or E1 rate
based upon the mode of operation.
MCLKT1
K1
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with accuracy better than
±50ppm and duty cycle within 40% to 60%. MCLKT1 is used in the T1 mode.
NOTES:
1.
All channels of the XRT83L38 must be operated at the same clock rate, either
T1, E1 or J1.
2.
See pin 26 description for further explanation for the usage of this pin.
3.
Internally pulled “Low” with a 50k
Ω resistor.
MCLKE1
J1
I
E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle of 40%
to 60% can be provided at this pin.
In systems that have only one master clock source available (E1 or T1), that clock
should be connected to both MCLKE1 and MCLKT1 inputs for proper operation.
NOTES:
1.
All channels of the XRT83L38 must be operated at the same clock rate, either
T1, E1 or J1.
2.
Internally pulled “Low” with a 50k
Ω resistor.
Disabled
Transmit
Receive
JA Path
JA BW Hz
--------
32/32
64/64
FIFO Size
-----
3
-----
10
1.5
0
1
JASEL1
0
1
0
1
JASEL0
T1
E1
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