- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1977 > XRT83L38IB-F (Exar Corporation)IC LIU T1/E1/J1 OCTAL 225BGA PDF資料下載
參數(shù)資料
| 型號： | XRT83L38IB-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 54/87頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 OCTAL 225BGA |
| 標準包裝： | 84 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 225-BGA |
| 供應(yīng)商設(shè)備封裝： | 225-BGA（19x19） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當前第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁
XRT83L38
55
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION
REGISTER ADDRESS
00000011
00010011
00100011
00110011
01000011
01010011
01100011
01110011
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
CHANNEL_4
CHANNEL_5
CHANNEL_6
CHANNEL_7
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
NLCDE1_n
Network Loop Code Detection Enable Bit 1:
This bit together with NLCDE0_n control the Loop-Code detec-
tion of each channel.
When NLCDE1 =”0” and NLCDE0 = “1” or NLCDE1 = “1” and
NLCDE0 = “0”, the chip is manually programmed to monitor
the receive data for the Loop-Up or Loop-Down code respec-
tively.When the presence of the “00001” or “001” pattern is
detected for more than 5 seconds, the status of the NLCD bit is
set to “1” and if the NLCD interrupt is enabled, an interrupt is
initiated.The Host has the option to control the Loop-Back
function manually.
Setting the NLCDE1 = “1” and NLCDE0 = “1” enables the
Automatic Loop-Code detection and Remote Loop-Back acti-
vation mode. As this mode is initiated, the state of the NLCD
interface bit is reset to “0” and the chip is programmed to mon-
itor the receive data for the Loop-Up code. If the “00001” pat-
tern is detected for longer than 5 seconds, the NLCD bit is set
“1”, Remote Loop-Back is activated and the chip is automati-
cally programmed to monitor the receive data for the Loop-
Down code. The NLCD bit stays set even after the chip stops
receiving the Loop-Up code. The Remote Loop-Back condition
is removed when the chip receives the Loop-Down code for
more than 5 seconds or if the Automatic Loop-Code detection
mode is terminated.
R/W
0
D6
NLCDE0_n
Network Loop Code Detection Enable Bit 0:
See description of D7 for function of this bit.
R/W
0
D5
CODES_n
Encoding and Decoding Select:
Writing a “0” to this bits selects HDB3 or B8ZS encoding and
decoding for channel number n. Writing “1” selects an AMI
coding scheme. This bit is only active when single rail mode is
selected.
R/W
0
NLCDE1
NLCDE0
0
1
0
1
Function
Disable Loop-code
detection
Detect Loop-Up code
in receive data
Detect Loop-Down
code in receive data
Automatic Loop-Code
detection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT83SH314IB-F | IC LIU T1/E1/J1 14CH 304TBGA |
| XRT83SH38IB-F | IC LIU SH T1/E1/J1 8CH 225BGA |
| XRT86L30IV-F | IC LIU/FRAMER TI/E1/J1 SGL 128LQ |
| XRT86VL30IV-F | IC FRAMR/LIU T1/E1/J1 QD 128LQFP |
| XRT86VL32IB-F | IC LIU/FRAMER T1/E1/J1 2CH 225BG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83L38IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SH314 | 制造商:EXAR 制造商全稱:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH314_0610 | 制造商:EXAR 制造商全稱:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH314ES | 功能描述:外圍驅(qū)動器與原件 - PCI 14 CHT1/E1LIU SH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SH314IB | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。