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參數(shù)資料
| 型號： | XRT81L27IV |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 10/30頁 |
| 文件大小： | 0K |
| 描述： | IC LIU EI 7CH 3.3V 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 應(yīng)用： | DECT |
| 接口： | 串行 |
| 電源電壓： | 3.3V |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT81L27
á
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
16
1.2
Description of the Command Registers
A listing of these Command Registers, their binary/
hex Addresses and their Bit-Formats are in Table 9.
All bits are reset to zero by activation of the Reset sig-
nal (RST, pin 3). All other registers (0111 through
1111) (0x07 through 0x0F) in the address range are
reserved.
TABLE 9: MICROPROCESSOR REGISTER ADDRESS AND CONTROL
REGISTER
ADDRESS
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
GLOBAL COMMAND CONTROL REGISTER (READ/WRITE)
0000/0x00
reserved
ARAOS
EXLOS
MUTE
SR/DR
CODE
RClkP
TClkP
CHANNEL CONTROL REGISTERS (READ/WRITE)
0001/0x01
reserved
LLB6
LLB5
LLB4
LLB3
LLB2
LLB1
LLB0
0010/0x02
reserved
RLB6
RLB5
RLB4
RLB3
RLB2
RLB1
RLB0
0011/0x03
reserved
ALB6
ALB5
ALB4
ALB3
ALB2
ALB1
ALB0
0100/0x04
reserved
TAOS6
TAOS5
TAOS4
TAOS3
TAOS2
TAOS1
TAOS0
0101/0x05
reserved
RAOS6
RAOS5
RAOS4
RAOS3
RAOS2
RAOS1
RAOS0
0110/0x06
reserved
PDTx6
PDTx5
PDTx4
PDTx3
PDTx2
PDTx1
PDTx0
TABLE 10: COMMAND CONTROL REGISTER - ADDRESS 0000 - HEX 0X00
(COMMON TO ALL SEVEN CHANNELS)
BIT #NAME
FUNCTION
REGISTER TYPE
6ARAOS
Automatic Receive All Ones:
Writing a "1" to this bit globally enables receive “all one data” insertion at
RPOS/RNEG upon receive LOS condition.
R/W
5
EXLOS
Extended LOS:
Writing a "1" to this bit extends the number of zeros at the receive input to
4096 bits before LOS is declared.
R/W
4MUTE
Receive Output Muting:
Writing a "1" to this bit mutes the receive data output at RPOS/RNEG to a
“Low” state upon LOS detection EXCEPT when AROAS is set.
R/W
3
SR/DR
Single-rail/Dual-rail:
Writing a "1" to this bit selects single-rail mode operation.
Writing a "0" to select dual-rail mode operation.
R/W
2CODE
Coding and Decoding:
In Single-Rail mode ONLY, selects HDB3 encoding and decoding when set.
Under all other conditions, AMI encoding and decoding is selected.
R/W
1
RClkP
Receive Clock Polarity:
Writing a "1" to this bit selects, receive output data to be updated on the rising
edge of RCLK and a "0" to update on the falling edge of RClk.
R/W
0TClkP
Transmit Clock Polarity:
Writing a "1" to this bit selects, input data to be sampled on the rising edge of
TClk and a "0" to sample on the falling edge of TClk.
R/W
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