TABLE
參數(shù)資料
型號： XRT75R12DIB-L
廠商： Exar Corporation
文件頁數(shù)： 68/133頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標準包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應商設備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12D
II
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
TABLE 6: JITTER TRANSFER SPECIFICATION/REFERENCES ..................................................................................................................... 29
4.3 JITTER ATTENUATOR ................................................................................................................................... 29
TABLE 7: JITTER TRANSFER PASS MASKS ............................................................................................................................................. 30
FIGURE 16. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE ...................................................................... 30
4.3.1 JITTER GENERATION................................................................................................................................................ 30
5.0 DIAGNOSTIC FEATURES ...................................................................................................................31
5.1 PRBS GENERATOR AND DETECTOR ......................................................................................................... 31
FIGURE 17. PRBS MODE ................................................................................................................................................................... 31
5.2 LOOPBACKS .................................................................................................................................................. 32
5.2.1 ANALOG LOOPBACK ................................................................................................................................................ 32
FIGURE 18. ANALOG LOOPBACK ........................................................................................................................................................... 32
5.2.2 DIGITAL LOOPBACK ................................................................................................................................................. 33
FIGURE 19. DIGITAL LOOPBACK ............................................................................................................................................................ 33
5.2.3 REMOTE LOOPBACK ................................................................................................................................................ 33
FIGURE 20. REMOTE LOOPBACK ........................................................................................................................................................... 33
5.3 TRANSMIT ALL ONES (TAOS) ...................................................................................................................... 34
FIGURE 21. TRANSMIT ALL ONES (TAOS) ............................................................................................................................................ 34
6.0 THE TRANSMITTER SECTION ...........................................................................................................35
FIGURE 22. TRANSMIT PATH BLOCK DIAGRAM....................................................................................................................................... 35
FIGURE 23. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75R12D (DUAL-RAIL DATA)............................................ 35
FIGURE 24. TRANSMITTER TERMINAL INPUT TIMING............................................................................................................................... 36
FIGURE 25. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) .................................................................. 36
6.1 TRANSMIT CLOCK ........................................................................................................................................ 37
6.2 B3ZS/HDB3 ENCODER .................................................................................................................................. 37
6.2.1 B3ZS ENCODING ....................................................................................................................................................... 37
FIGURE 27. B3ZS ENCODING FORMAT ................................................................................................................................................. 37
6.2.2 HDB3 ENCODING ....................................................................................................................................................... 37
FIGURE 26. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED).................................................................................... 37
FIGURE 28. HDB3 ENCODING FORMAT ................................................................................................................................................. 38
6.3 TRANSMIT PULSE SHAPER ......................................................................................................................... 38
FIGURE 29. TRANSMIT PULSE SHAPE TEST CIRCUIT.............................................................................................................................. 38
6.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................. 38
6.4 E3 LINE SIDE PARAMETERS ........................................................................................................................ 39
FIGURE 30. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703 ............................................................................. 39
TABLE 8: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS .............................................................. 39
FIGURE 31. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ................................. 40
TABLE 9: STS-1 PULSE MASK EQUATIONS ........................................................................................................................................... 40
TABLE 10: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)................................... 41
FIGURE 32. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ......................................................................... 42
TABLE 11: DS3 PULSE MASK EQUATIONS............................................................................................................................................. 42
TABLE 12: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ...................................... 43
6.5 TRANSMIT DRIVE MONITOR ........................................................................................................................ 44
FIGURE 33. TRANSMIT DRIVER MONITOR SET-UP................................................................................................................................... 44
6.6 TRANSMITTER SECTION ON/OFF ............................................................................................................... 44
7.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................45
TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE .......................................................................................................... 45
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK ........................................................................ 45
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 46
TABLE 14: XRT75R12D MICROPROCESSOR INTERFACE SIGNALS ......................................................................................................... 46
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 47
FIGURE 35. ASYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................................. 47
TABLE 15: ASYNCHRONOUS TIMING SPECIFICATIONS............................................................................................................................. 48
FIGURE 36. SYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................................... 48
TABLE 16: SYNCHRONOUS TIMING SPECIFICATIONS............................................................................................................................... 49
7.3 REGISTER MAP ............................................................................................................................................. 50
TABLE 17: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R12D ........................................................................................... 50
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................................ 59
TABLE 18: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS........................................................................................................ 59
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................................... 59
TABLE 19: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) ..................................................... 59
TABLE 20: APS/REDUNDANCY RECIEVE CONTROL REGISTER - CR8 (ADDRESS LOCATION = 0X08) ....................................................... 60
TABLE 21: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR128 (ADDRESS LOCATION = 0X80) ................................................. 60
TABLE 22: APS/REDUNDANCY RECIEVE CONTROL REGISTER - CR136 (ADDRESS LOCATION = 0X88) ................................................... 61
TABLE 23: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR96 (ADDRESS LOCATION = 0X60) ......................................................... 62
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