參數(shù)資料
型號： XRT75R12DIB-L
廠商： Exar Corporation
文件頁數(shù)： 31/133頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12D
122
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
Figure 69 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN B.
Hence, MAJOR PATTERN B consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses.
These 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 STS-1 (or 51.84MHz)
clock periods.
PUTTING THE PATTERNS TOGETHER
Finally, the DS3 to OC-N Mapper IC clock output is reproduced by doing the following.
MAJOR PATTERN A is transmitted two times (repeatedly).
After the second transmission of MAJOR PATTERN A, MAJOR PATTERN B is transmitted once.
Then the whole process repeats.
Throughout the remainder of this document, we will refer to this particular pattern as the "SUPER PATTERN".
Figure 70 presents an illustration of this "SUPER PATTERN" which is output via the Mapper IC.
CROSS-CHECKING OUR DATA
Each SUPER PATTERN consists of (621 + 621 + 622) = 1864 clock pulses.
The total amount of time, which is required for the "DS3 to OC-N Mapper" IC to transmit this SUPER
PATTERN is (720 + 720 + 720) = 2160 "STS-1" clock periods.
This amount to a period of (2160/51.84MHz) = 41,667ns.
In a period of 41, 667ns, the LIU (when configured to operate in the DS3 Mode), will output a total (41,667ns
x 44,736,000) = 1864 uniformly spaced DS3 clock pulses.
Hence, the number of clock pulses match.
APPLYING THE SUPER PATTERN TO THE LIU
Whenever the LIU is configured to operate in a "SONET De-Sync" application, the device will accept a
continuous string of the above-defined SUPER PATTERN, via the TCLK input pin (along with the
corresponding data). The channel within the LIU (which will be configured to operate in the "DS3" Mode) will
FIGURE 69. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B
FIGURE 70. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC
PATTERN P1
PATTERN P2
Repeats 63 Times
Repeats 35 Times
PATTERN P3
Transmitted 1 Time
PATTERN A
PATTERN B
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